Xilinx 1.8 manual Quickstart Example Design, Simulation Design Overview

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Chapter 3

Quickstart Example Design

This chapter provides an overview of the Endpoint Block Plus for PCI Express example design (both single and dual core) and instructions for generating the core. It also includes information about simulating and implementing the example design using the provided demonstration test bench.

Overview

The example simulation design consists of two discrete parts:

•The Downstream Port Model, a test bench that generates, consumes, and checks PCI Express bus traffic.

•The Programmed Input Output (PIO) example design, a completer application for PCI Express. The PIO example design responds to Read and Write requests to its memory space and can be synthesized for testing in hardware.

Simulation Design Overview

For the simulation design, transactions are sent from the Downstream Port Model to the Block Plus core and processed by the PIO example design. Figure 3-1illustrates the simulation design provided with the Block Plus core. For more information about the Downstream Port Model, see Appendix B, “Downstream Port Model Test Bench,” in the LogiCORE IP Endpoint Block Plus for PCI Express User Guide.

Endpoint Block Plus v1.8 for PCI Express

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Preface About This Guide Online DocumentAbout the Core IntroductionSystem Requirements Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreFeedback DocumentIntroduction Before you Begin Licensing the CoreLicense Options Simulation OnlyObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview Quickstart Example Design 1Simulation Example Design Block DiagramExample Design Elements Implementation Design OverviewOverview 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreSimulating the Example Design Setting up for SimulationRunning the Simulation Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc Component name/implement Component name/exampledesign4Example Design Directory Name Description 5Implement Directory Name DescriptionComponent name/simulation Implement/results6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/functional Simulation/dsport8dsport Directory Name Description 9Functional Directory Name DescriptionSimulation/tests Dual Core Example DesignDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 11Example Design Directory Name Description Exampledesign/dualcore12Dual Core Directory Name Description 13Simulation Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionUser Constraints Files Package ConstraintsWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations