Xilinx 1.8 manual Component name/exampledesign, Component name/implement

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Chapter 3: Quickstart Example Design

<component name>/example_design

The example design directory contains the example design files provided with the core.

Table 3-4:Example Design Directory

Name	Description

<project_dir>/<component_name>/example_design

pci_exp_8_lane_64b_ep.v	Verilog top-level port list, applicable
pci_exp_4_lane_64b_ep.v	to the 8-lane, 4-lane, and 1-lane
pci_exp_1_lane_64b_ep.v	endpoint design, respectively.
	endpoint design, respectively.

<filename>.ucf	Example design UCF. Filename
	varies by lane-width, part, and
	package selected.

xilinx_pci_exp_8_lane_ep_product.v	Enables Block Plus 8-lane, 4-lane,
xilinx_pci_exp_4_lane_ep_product.v	and 1-lane cores, respectively, in the
xilinx_pci_exp_1_lane_ep_product.v	test bench.

xilinx_pci_exp_8_lane_ep.v	Verilog or VHDL top-level PIO
xilinx_pci_exp_4_lane_ep.v	example design files for 8-lane, 4-
xilinx_pci_exp_1_lane_ep.v	lane, and 1-lane cores.
xilinx_pci_exp_ep.vhd

pci_exp_64b_app.v[hd]
EP_MEM.v[hd]
PIO.v[hd]
PIO_EP.v[hd]	PIO example design files.
PIO_EP_MEM_ACCESS.v[hd]	PIO example design files.
PIO_TO_CTRL.v[hd]
PIO_64.v
PIO_64_RX_ENGINE.v[hd]
PIO_64_TX_ENGINE.v[hd]

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<component name>/implement

The implement directory contains the core implementation script files.

Table 3-5:Implement Directory

	Name	Description

	<project_dir>/<component_name>/implement

	xst.scr	XST synthesis script.

	implement.bat	DOS and Linux implementation scripts.
	implement.sh

	synplify.prj	Synplify synthesis script.

	xilinx_pci_exp_1_lane_ep_inc.xst	XST project file for 1-lane, 4-lane, and 8-lane
	xilinx_pci_exp_4_lane_ep_inc.xst	XST project file for 1-lane, 4-lane, and 8-lane
	xilinx_pci_exp_4_lane_ep_inc.xst	example design, respectively.
	xilinx_pci_exp_8_lane_ep_inc.xst	example design, respectively.
	xilinx_pci_exp_8_lane_ep_inc.xst

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22	www.xilinx.com	Endpoint Block Plus v1.8 for PCI Express
		UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Online Document Preface About This GuideSystem Requirements IntroductionAbout the Core Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreDocument FeedbackIntroduction License Options Licensing the CoreBefore you Begin Simulation OnlyObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview 1Simulation Example Design Block Diagram Quickstart Example DesignExample Design Elements Implementation Design OverviewOverview Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenSimulating the Example Design Setting up for SimulationRunning the Simulation Windows Implementing the Example DesignImplementing the Example Design LinuxDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc 4Example Design Directory Name Description Component name/exampledesignComponent name/implement 5Implement Directory Name Description6Results Directory Name Description Implement/resultsComponent name/simulation 7Simulation Directory Name Description8dsport Directory Name Description Simulation/dsportSimulation/functional 9Functional Directory Name DescriptionDual Core Example Design Dual Core Example DesignSimulation/tests 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 12Dual Core Directory Name Description Exampledesign/dualcore11Example Design Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionWrapper File Usage Package ConstraintsUser Constraints Files Device/Part NumberAppendix Appendix Additional Design Considerations