Xilinx 1.8 manual Introduction

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Chapter 1: Introduction

10	www.xilinx.com	Endpoint Block Plus v1.8 for PCI Express
		UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Online Document Preface About This GuideSystem Requirements IntroductionAbout the Core Recommended Design ExperienceFeedback Additional Core ResourcesTechnical Support CoreDocument FeedbackIntroduction License Options Licensing the CoreBefore you Begin Simulation OnlyObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview 1Simulation Example Design Block Diagram Quickstart Example DesignExample Design Elements Implementation Design OverviewOverview Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenSimulating the Example Design Setting up for SimulationRunning the Simulation Windows Implementing the Example DesignImplementing the Example Design LinuxDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc 4Example Design Directory Name Description Component name/exampledesignComponent name/implement 5Implement Directory Name Description6Results Directory Name Description Implement/resultsComponent name/simulation 7Simulation Directory Name Description8dsport Directory Name Description Simulation/dsportSimulation/functional 9Functional Directory Name DescriptionDual Core Example Design Dual Core Example DesignSimulation/tests 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 12Dual Core Directory Name Description Exampledesign/dualcore11Example Design Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionWrapper File Usage Package ConstraintsUser Constraints Files Device/Part NumberAppendix Appendix Additional Design Considerations