R
Chapter 3: Quickstart Example Design
xilinx_dual_pci_exp_ep
xilinx_pci_exp_primary_ep
pci_exp_64b_app
PIO
Endpoint
Core
xilinx_pci_exp_secondary_ep
pci_exp_64b_app
PIO
Endpoint
Core
Figure 3-6: Dual Core Design Block Diagram
Dual Core Directory Structure and File Contents
When generating the Block Plus core with the
For the dual core example design, in addition to the source files, simulation scripts, and implementation files generated in the <project name>/<component name> directory specified by the user, the following directories and associated files are used:
<component name>/example_design
Dual core Verilog or VHDL design files
example_design/dual_core
Implementation script files
<component name>/simulation
Simulation Verilog or VHDL source files
simulation/functional
Simulation scripts
<component name>/implement
Implementation scripts
26 | www.xilinx.com | Endpoint Block Plus v1.8 for PCI Express |
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| UG343 June 27, 2008 |