Xilinx 1.8 manual Implementing the Example Design, Windows, Linux

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Implementing the Example Design

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2.Run the script that corresponds to your simulation tool using one of the following:

•VCS: simulate_vcs.sh

•Cadence IUS: simulate_ncsim.sh

•ModelSim: vsim -do simulate_mti.do

Implementing the Example Design

After generating the core, the netlists and the example design can be processed using the Xilinx implementation tools. The generated output files include scripts to assist you in running the Xilinx software.

To implement the example design:

Open a command prompt or terminal window and type the following:

Windows

ms-dos>cd <project_dir>\<component_name>\implement ms-dos>implement.bat

Linux

%cd <project_dir>/<component_name>/implement

%./implement.sh

These commands execute a script that synthesizes, builds, maps, and place-and-routes the example design, and then generates a post-par simulation model for use in timing simulation. The resulting files are placed in the results directory and execute the following processes:

1.Removes data files from the previous runs.

2.Synthesizes the example design using either Synplicity Synplify or XST. - The core is instanced as a black box within the example design.

3.ngdbuild. Builds a Xilinx design database for the example design. Inputs:

Part-Package-Speed Grade selection: XC5VLX50T-FF1136-1

Example design UCF:

xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1.ucf

4.map: Maps design to the selected FPGA using the constraints provided.

5.par: Places cells onto FPGA resources and routes connectivity.

6.trce: Performs static timing analysis on design using constraints specified.

7.netgen: Generates a logical Verilog HDL or VHDL representation of the design and an SDF file for post-layout verification.

8.bitgen: Generates a bitstream file for programming the FPGA.

The following FPGA implementation related files are generated in the results directory:

•routed.bit

FPGA configuration information.

•routed.v[hd]

Verilog or VHDL functional Model.

Endpoint Block Plus v1.8 for PCI Express

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Preface About This Guide Online DocumentRecommended Design Experience IntroductionAbout the Core System RequirementsCore Additional Core ResourcesTechnical Support FeedbackFeedback DocumentIntroduction Simulation Only Licensing the CoreBefore you Begin License OptionsObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview Quickstart Example Design 1Simulation Example Design Block DiagramExample Design Elements Implementation Design OverviewOverview 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreSimulating the Example Design Setting up for SimulationRunning the Simulation Linux Implementing the Example DesignImplementing the Example Design WindowsDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc 5Implement Directory Name Description Component name/exampledesignComponent name/implement 4Example Design Directory Name Description7Simulation Directory Name Description Implement/resultsComponent name/simulation 6Results Directory Name Description9Functional Directory Name Description Simulation/dsportSimulation/functional 8dsport Directory Name Description10Tests Directory Name Description Dual Core Example DesignSimulation/tests Dual Core Example DesignDual Core Directory Structure and File Contents 13Simulation Directory Name Description Exampledesign/dualcore11Example Design Directory Name Description 12Dual Core Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionDevice/Part Number Package ConstraintsUser Constraints Files Wrapper File UsageAppendix Appendix Additional Design Considerations
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