Xilinx 1.8 Package Constraints, User Constraints Files, Wrapper File Usage, Device/Part Number

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Appendix

Additional Design Considerations

Package Constraints

This appendix describes design considerations specific to the Endpoint Block Plus for PCIe core. Table A-1lists the smallest supported device and interface combinations for the Block Plus core.

Table A-1:Supported Device and Interface Combinations

Smallest Supported

Data Bus Width/Speed

Wrapper File

Device/Part Number

 

 

 

 

 

XC5VLX20T FF323-1

Width: 64-bit Port

xilinx_pci_exp_1_lane_ep.v

 

Speed: 62.5 MHz

 

 

 

 

XC5VLX20T FF323-1

Width: 64-bit Port

xilinx_pci_exp_4_lane_ep.v

 

Speed: 125 MHz

 

 

 

 

XC5VLX30T FF665-1

Width: 64-bit Port

xilinx_pci_exp_8_lane_ep.v

 

Speed: 250 MHz

 

 

 

 

User Constraints Files

The user constraints file (UCF) contains various constraints required for the Block Plus core. The user constraints file must always be used while processing a design and is specific to the target device. Based on the chosen lane width, part, and package, a suitable UCF is created by CORE Generator.

Wrapper File Usage

The wrapper contains an instance of the Block Plus core. When starting a new design, modify this wrapper to include all I/O elements and modules. One of the following files is generated by the CORE Generator based on the chosen lane width.

<project_dir>/<component_name>/example_design/xilinx_pci_exp_1_lane_ep.v <project_dir>/<component_name>/example_design/xilinx_pci_exp_4_lane_ep.v <project_dir>/<component_name>/example_design/xilinx_pci_exp_8_lane_ep.v

Endpoint Block Plus v1.8 for PCI Express

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Preface About This Guide Online DocumentAbout the Core IntroductionSystem Requirements Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreFeedback DocumentIntroduction Before you Begin Licensing the CoreLicense Options Simulation OnlyLicensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview Quickstart Example Design 1Simulation Example Design Block DiagramOverview Implementation Design OverviewExample Design Elements 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreRunning the Simulation Setting up for SimulationSimulating the Example Design Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Component name/doc Project directoryProject directory/component name Component name/implement Component name/exampledesign4Example Design Directory Name Description 5Implement Directory Name DescriptionComponent name/simulation Implement/results6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/functional Simulation/dsport8dsport Directory Name Description 9Functional Directory Name DescriptionSimulation/tests Dual Core Example DesignDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 11Example Design Directory Name Description Exampledesign/dualcore12Dual Core Directory Name Description 13Simulation Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionUser Constraints Files Package ConstraintsWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations
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