Xilinx 1.8 manual Generating the Core, 5Endpoint Block Plus Main Screen

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Generating the Core

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4.Set the project options:

From the Part tab, select the following options:

•Family: Virtex5

•Device: xc5vlx50t

•Package: ff1136

•Speed Grade: -1

Note: If an unsupported silicon device is selected, the core is dimmed (unavailable) in the list of cores.

From the Generation tab, select the following parameters, and then click OK.

•Design Entry. Select either VHDL or Verilog.

•Vendor. Select Synplicity® or ISE (for XST).

5.Locate the core in the selection tree under Standard Bus Interfaces/PCI Express; then double-click the core name to display the Block Plus main screen.

Figure 3-5:Endpoint Block Plus Main Screen

6.In the Component Name field, enter a name for the core. <component_name> is used in this example.

7.Click Finish to generate the core using the default parameters. The core and its supporting files, including the PIO example design and Downstream Port Model test bench, are generated in the project directory.

For detailed information about the example design files and directories see “Directory Structure and File Contents,” page 20.

Endpoint Block Plus v1.8 for PCI Express

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UG343 June 27, 2008

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Contents UG343 June 27 LogiCORE IP Endpoint Block Plus v1.8 for PCI ExpressDate Version Revision Revision HistoryTable of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Preface About This Guide Online DocumentAbout the Core IntroductionSystem Requirements Recommended Design ExperienceTechnical Support Additional Core ResourcesFeedback CoreFeedback DocumentIntroduction Before you Begin Licensing the CoreLicense Options Simulation OnlyLicensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview Quickstart Example Design 1Simulation Example Design Block DiagramOverview Implementation Design OverviewExample Design Elements 3New Project Dialog Box Generating the Core5Endpoint Block Plus Main Screen Generating the CoreRunning the Simulation Setting up for SimulationSimulating the Example Design Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Component name/doc Project directoryProject directory/component name Component name/implement Component name/exampledesign4Example Design Directory Name Description 5Implement Directory Name DescriptionComponent name/simulation Implement/results6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/functional Simulation/dsport8dsport Directory Name Description 9Functional Directory Name DescriptionSimulation/tests Dual Core Example DesignDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents 11Example Design Directory Name Description Exampledesign/dualcore12Dual Core Directory Name Description 13Simulation Directory Name Description15Implement Directory Name Description 14Functional Directory Name DescriptionUser Constraints Files Package ConstraintsWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations