Xilinx 1.8 manual 14Functional Directory Name Description, 15Implement Directory Name Description

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Chapter 3: Quickstart Example Design

simulation/functional

The functional directory contains the dual core example design simulation scripts.

Table 3-14:Functional Directory

Name	Description

simulate_dual_mti.do	ModelSim simulation script.

simulate_dual_ncsim.sh	Cadence IUS simulation script.

simulate_dual_vcs.sh	VCS simulation script.

board_dual_rtl_x0*.f	List of files for RTL simulations.

board_dual_rtl_x0*_ncv.f	List of files for RTL simulations.

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<component name>/implement

The implement directory contains the dual core example design implementation script files.

Table 3-15:Implement Directory

Name	Description

implement_dual.sh	Linux implementation script.

xst_dual.scr	XST synthesis script.

xilinx_dual_pci_exp_*_lane_ep_inc.xst	XST project file for 1-lane, 4-lane, and 8-
	lane example design, respectively.

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Simulation and implementation commands for the dual core example design are similar to the single core example design commands. To modify simulation and implementation commands for the dual core example design, see “Simulating the Example Design,” page 18, and “Implementing the Example Design,” page 19 and replace them with the respective dual core names.

The simulation test bench used with the dual core example design makes use of the downstream port TLP generator from the example design. Because the test bench has only one downstream port, only one of the two PCI Express Block cores can be sent TLPs per simulation run. The downstream port simulates the primary PCI Express Block core by default. To simulate the secondary PCI Express block, you can modify board.v[hd].

28	www.xilinx.com	Endpoint Block Plus v1.8 for PCI Express
		UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations About This Guide ContentsConventions Online Document Preface About This GuideIntroduction About the CoreSystem Requirements Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreDocument FeedbackIntroduction Licensing the Core Before you BeginLicense Options Simulation OnlyObtaining Your License Installing Your License FileLicensing the Core Overview Quickstart Example DesignSimulation Design Overview 1Simulation Example Design Block Diagram Quickstart Example DesignExample Design Elements Implementation Design OverviewOverview Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenSimulating the Example Design Setting up for SimulationRunning the Simulation Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Project directory/component name Project directoryComponent name/doc Component name/exampledesign Component name/implement4Example Design Directory Name Description 5Implement Directory Name DescriptionImplement/results Component name/simulation6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/dsport Simulation/functional8dsport Directory Name Description 9Functional Directory Name DescriptionDual Core Example Design Simulation/testsDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents Exampledesign/dualcore 11Example Design Directory Name Description12Dual Core Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionPackage Constraints User Constraints FilesWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations