Xilinx 1.8 manual Directory Structure and File Contents

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Chapter 3: Quickstart Example Design

•routed.sdf

Timing model Standard Delay File.

•mapped.mrp

Xilinx map report.

•routed.par

Xilinx place and route report.

•routed.twr

Xilinx timing analysis report.

The script file starts from an EDIF/NGC file and results in a bitstream file. It is possible to use the Xilinx ISE GUI to implement the example design. However, the GUI flow is not presented in this document.

Directory Structure and File Contents

The Endpoint Block Plus for PCIe example design directories and their associated files are defined in the sections that follow. Click a directory name to go to the desired directory and its associated files.

Example Design

<project directory>

Top-level project directory; name is user-defined

<project directory>/<component name>

Core release notes readme file

<component name>/doc

Product documentation

<component name>/example_design

Verilog or VHDL design files

<component name>/implement

Implementation script files

implement/results

Results directory, created after implementation scripts are run, and contains implement script results

<component name>/simulation

Simulation scripts

simulation/dsport

Simulation files

simulation/functional

Functional simulation files

simulation/tests

Test command files

Note: For the dual core example design directory structure and file contents, see “Dual Core Directory Structure and File Contents,” page 26.

20	www.xilinx.com	Endpoint Block Plus v1.8 for PCI Express
		UG343 June 27, 2008

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Contents LogiCORE IP Endpoint Block Plus v1.8 for PCI Express UG343 June 27Revision History Date Version RevisionTable of Contents Appendix Additional Design Considerations Conventions ContentsAbout This Guide Online Document Preface About This GuideIntroduction About the CoreSystem Requirements Recommended Design ExperienceAdditional Core Resources Technical SupportFeedback CoreDocument FeedbackIntroduction Licensing the Core Before you BeginLicense Options Simulation OnlyLicensing the Core Installing Your License FileObtaining Your License Simulation Design Overview Quickstart Example DesignOverview 1Simulation Example Design Block Diagram Quickstart Example DesignOverview Implementation Design OverviewExample Design Elements Generating the Core 3New Project Dialog BoxGenerating the Core 5Endpoint Block Plus Main ScreenRunning the Simulation Setting up for SimulationSimulating the Example Design Implementing the Example Design Implementing the Example DesignWindows LinuxDirectory Structure and File Contents Component name/doc Project directoryProject directory/component name Component name/exampledesign Component name/implement4Example Design Directory Name Description 5Implement Directory Name DescriptionImplement/results Component name/simulation6Results Directory Name Description 7Simulation Directory Name DescriptionSimulation/dsport Simulation/functional8dsport Directory Name Description 9Functional Directory Name DescriptionDual Core Example Design Simulation/testsDual Core Example Design 10Tests Directory Name DescriptionDual Core Directory Structure and File Contents Exampledesign/dualcore 11Example Design Directory Name Description12Dual Core Directory Name Description 13Simulation Directory Name Description14Functional Directory Name Description 15Implement Directory Name DescriptionPackage Constraints User Constraints FilesWrapper File Usage Device/Part NumberAppendix Appendix Additional Design Considerations