Silicon Laboratories
SI4421
manual
Si4421, VDI Logic Diagram
Specification
AC Characteristics Receiver
Functional Block Diagram
Wake-UpTimer
FIFO and Reset Mode Command
Control Commands
Configuration Setting Command
RF Power Amplifier PA
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Contents
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
FEATURES
TYPICAL APPLICATIONS
Data Filtering and Clock Recovery
DETAILED FEATURE-LEVELDESCRIPTION
RF Power Amplifier PA
Si4421
Data Validity Blocks
Low Battery Voltage Detector
Wake-UpTimer
Crystal Oscillator
Type
Si4421 PACKAGE PIN DEFINITIONS
Name
Function
Name
Si4421
Internal Pin Connections
Internal connection
Note These pins can be left floating
PIN6 Logic Diagram FSK / DATA / nFFS
PIN10 Logic Diagram nRES I/O
Si4421
Recommended supply decoupling capacitor values
Si4421
Typical Application
Pin Function vs. Operation Mode
Si4421 GENERAL DEVICE SPECIFICATIONS
Absolute Maximum Ratings non-operating
Recommended Operating Range
ELECTRICAL SPECIFICATION
DC Characteristics
Si4421
AC Characteristics PLL parameters
AC Characteristics Receiver
Si4421
AC Characteristics Turn-on/Turnaroundtimings
Si4421
AC Characteristics Transmitter
AC Characteristics Others
Si4421
Note 10 By design
Si4421 CONTROL INTERFACE
Timing Specification
Timing Diagram
Control Commands
Control Register Default Values
Si4421
2. Power Management Command
Description of the Control Commands
Configuration Setting Command
Si4421
Logic connections between power control bits
Si4421
5. Receiver Control Command
Frequency Setting Command
4. Data Rate Command
Si4421
VDI Logic Diagram
Si4421
6. Data Filter Command
Si4421
7.FIFO and Reset Mode Command
Si4421
10. AFC Command
8. Synchron Pattern Command
9. Receiver FIFO Read Command
Si4421
Si4421
Bit 5-4rl1 to rl0
11. TX Configuration Control Command
Frequency Setting Command
Si4421
13. Transmitter Register Write Command
12. PLL Setting Command
Si4421
14. Wake-UpTimer Command
15.Low Duty-CycleCommand
Si4421
Vlb= 2.25 + V · 0.1 V Clock divider configuration
Si4421
17. Status Read Command
Si4421
Bit Name
Si4421 INTERRUPT HANDLING
TX REGISTER BUFFERED DATA TRANSMISSION
Si4421
Si4421
Typical TX register usage
Si4421 RX FIFO BUFFERED DATA READ
RECOMMENDED PACKET STRUCTURES
Bit Rate 9.6 kbps
Si4421 CRYSTAL SELECTION GUIDELINES
Bit Rate 2.4 kbps
Bit Rate 38.4 kbps
Si4421 RX-TXALIGNMENT PROCEDURES
Si4421 RESET MODES
SW Reset Command
Sensitive Reset Enabled, Ripple on Vdd
FIFO and Reset Mode Command page
Si4421
Si4421 TYPICAL PERFORMANCE CHARACTERISTICS
Channel Selectivity and Blocking
Si4421
BER Curves in 433 MHz Band
BER Curves in 868 MHz Band
Si4421
434 MHz
Evaluation Board with 50 Ohm Matching Network
Si4421 REFERENCE DESIGNS
Schematics
Frequency Dependent Component Values
Si4421
PCB Layout Top View Bottom View
Evaluation Board with Resonant PCB Antenna BIFA
Schematics
Si4421
Frequency Dependent Component Values
Si4421
PCB Layout Antenna designed for 868/915 MHz band
Top View Bottom View
Si4421 PACKAGE INFORMATION
16-pinTSSOP
See Detail “A” Section B-B
Demo Boards and Development Kits
RELATED PRODUCTS AND DOCUMENTS
Si4421 Universal ISM Band FSK Transceiver
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Si4421
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