Silicon Laboratories SI4421 manual Si4421, Vlb= 2.25 + V · 0.1 V Clock divider configuration

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Si4421

Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers:

16. Low Battery Detector and Microcontroller Clock Divider Command

Bit	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	POR
	1	1	0	0	0	0	0	0	d2	d1	d0	0	v3	v2	v1	v0	C000h

The 4-bit parameter (v3 to v0) represents the value V, which defines the threshold voltage Vlb of the detector:

Vlb= 2.25 + V · 0.1 [V] Clock divider configuration:

	d2		d1		d0		Clock Output
							Frequency [MHz]

0		0		0		1
0		0		1		1.25
0		1		0		1.66
0		1		1		2
1		0		0		2.5
1		0		1		3.33
1		1		0		5
1		1		1		10

The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management Command (page 15).

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Contents DESCRIPTION FUNCTIONAL BLOCK DIAGRAMFEATURES TYPICAL APPLICATIONSData Filtering and Clock Recovery DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Si4421Data Validity Blocks Low Battery Voltage DetectorWake-UpTimer Crystal OscillatorType Si4421 PACKAGE PIN DEFINITIONSName FunctionName Si4421Internal Pin Connections Internal connectionNote These pins can be left floating PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Si4421Recommended supply decoupling capacitor values Si4421Typical Application Pin Function vs. Operation ModeRecommended Operating Range Si4421 GENERAL DEVICE SPECIFICATIONSAbsolute Maximum Ratings non-operating Si4421 ELECTRICAL SPECIFICATIONDC Characteristics Si4421 AC Characteristics PLL parametersAC Characteristics Receiver AC Characteristics Turn-on/Turnaroundtimings Si4421AC Characteristics Transmitter AC Characteristics OthersSi4421 Note 10 By designTiming Diagram Si4421 CONTROL INTERFACETiming Specification Si4421 Control CommandsControl Register Default Values 2. Power Management Command Description of the Control CommandsConfiguration Setting Command Si4421Logic connections between power control bits Si44215. Receiver Control Command Frequency Setting Command4. Data Rate Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si442110. AFC Command 8. Synchron Pattern Command9. Receiver FIFO Read Command Si4421Si4421 Bit 5-4rl1 to rl0Si4421 11. TX Configuration Control CommandFrequency Setting Command Si4421 13. Transmitter Register Write Command12. PLL Setting Command Si4421 14. Wake-UpTimer Command15.Low Duty-CycleCommand Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421Bit Name 17. Status Read CommandSi4421 Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESBit Rate 9.6 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES SW Reset Command Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingBER Curves in 868 MHz Band Si4421BER Curves in 433 MHz Band Si4421 434 MHzEvaluation Board with 50 Ohm Matching Network Si4421 REFERENCE DESIGNSSchematics Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewEvaluation Board with Resonant PCB Antenna BIFA SchematicsSi4421 Frequency Dependent Component ValuesTop View Bottom View Si4421PCB Layout Antenna designed for 868/915 MHz band See Detail “A” Section B-B Si4421 PACKAGE INFORMATION16-pinTSSOP Demo Boards and Development Kits RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Related ResourcesSi4421