Silicon Laboratories SI4421 Si4421, TX Configuration Control Command, Frequency Setting Command

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11. TX Configuration Control Command

Si4421

There are four operation modes:

1.(a1=0, a0=0) Automatic operation of the AFC is off. Strobe bit can be controlled by the microcontroller.

2.(a1=0, a0=1) The circuit measures the frequency offset only once after power up. This way, extended TX-RX distance can be achieved. In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal tolerances. This method allows for the use of cheaper quartz in the application and provides protection against tracking an interferer.

3.(a1=1, a0=0) The frequency offset is calculated automatically and the center frequency is corrected when the VDI is high. The calculated value is dropped when the VDI goes low. To improve the efficiency of the AFC calculation two methods are recommended:

a.The transmit package should start with a low effective baud rate pattern (i.e.: 00110011) because it is easier to receive. The circuit automatically measures the frequency offset during this initial pattern and changes the receiving frequency accordingly. The further part of the package will be received by the corrected frequency settings.

b.The transmitter sends the first part of the packet with a step higher deviation than required during normal operation to ease the receiving. After the frequency shift was corrected, the deviation can be reduced.

In both cases (3a and 3b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use this “drop offset” mode when the receiver communicates with more than one transmitter.

4.(a1=1, a0=1) It is similar to mode 3, but suggested to use when a receiver operates with only one transmitter. After a complete measuring cycle, the measured value is kept independently of the state of the VDI signal. When the receiver is paired with only one transmitter, it is possible to use this “keep offset” mode. In this case, the DRSSI limit should be selected carefully to minimize the range hysteresis.

11. TX Configuration Control Command

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

 

1

0

0

1

1

0

0

mp

m3

m2

m1

m0

0

p2

p1

p0

9800h

Bits 8-4 (mp, m3 to m0): FSK modulation parameters:

The resulting output frequency can be calculated as:

 

fout = f0 + (-1)SIGN· (M + 1) · (15 kHz)

Pout

 

 

 

 

 

 

 

 

where:

 

 

 

 

 

 

 

 

 

df fsk

df fsk

 

 

 

f0 is the channel center frequency (see the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Frequency Setting Command)

 

 

 

 

 

 

 

 

 

 

 

 

 

M is the four bit binary number <m3 : m0>

 

 

 

 

 

 

 

 

 

 

 

SIGN = (mp) XOR FSK

 

 

 

 

 

 

 

 

 

 

 

f out

 

 

 

 

 

 

 

 

f

0

 

 

 

 

 

 

 

 

 

 

Note: For the optimal FSK modulation settings at different

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

data rates see the table on page 37.

 

 

mp=0 and FSK=0

 

 

mp=0 and FSK=1

Bits 2-0 (p2 to p0): Output power:

 

 

 

 

or

 

 

or

 

 

 

 

mp=1 and FSK=1

 

 

mp=1 and FSK=0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

p2

p1

p0

Relative Output Power [dB]

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

0

 

Note: FSK represents the value of the actual data bit.

 

 

 

 

 

 

 

 

0

0

1

 

-2.5

 

 

0

1

0

 

-5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

 

-7.5

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

 

-10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

1

 

-12.5

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

 

-15

 

 

 

 

 

 

 

 

 

 

 

 

1

1

1

 

-17.5

 

 

 

 

 

 

 

 

 

 

 

Note: The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance. (See: Antenna Application Note: IA ISM-AN1)

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Contents TYPICAL APPLICATIONS FUNCTIONAL BLOCK DIAGRAMFEATURES DESCRIPTIONSi4421 DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Data Filtering and Clock RecoveryCrystal Oscillator Low Battery Voltage DetectorWake-UpTimer Data Validity BlocksFunction Si4421 PACKAGE PIN DEFINITIONSName TypeInternal connection Si4421Internal Pin Connections NameSi4421 PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Note These pins can be left floatingPin Function vs. Operation Mode Si4421Typical Application Recommended supply decoupling capacitor valuesRecommended Operating Range Si4421 GENERAL DEVICE SPECIFICATIONSAbsolute Maximum Ratings non-operating Si4421 ELECTRICAL SPECIFICATIONDC Characteristics Si4421 AC Characteristics PLL parametersAC Characteristics Receiver AC Characteristics Others Si4421AC Characteristics Transmitter AC Characteristics Turn-on/TurnaroundtimingsNote 10 By design Si4421Timing Diagram Si4421 CONTROL INTERFACETiming Specification Si4421 Control CommandsControl Register Default Values Si4421 Description of the Control CommandsConfiguration Setting Command 2. Power Management CommandSi4421 Logic connections between power control bitsSi4421 Frequency Setting Command4. Data Rate Command 5. Receiver Control CommandSi4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode CommandSi4421 8. Synchron Pattern Command9. Receiver FIFO Read Command 10. AFC CommandBit 5-4rl1 to rl0 Si4421Si4421 11. TX Configuration Control CommandFrequency Setting Command Si4421 13. Transmitter Register Write Command12. PLL Setting Command Si4421 14. Wake-UpTimer Command15.Low Duty-CycleCommand Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configurationBit Name 17. Status Read CommandSi4421 Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 38.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 9.6 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Si4421 Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page SW Reset CommandChannel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSBER Curves in 868 MHz Band Si4421BER Curves in 433 MHz Band 434 MHz Si4421Frequency Dependent Component Values Si4421 REFERENCE DESIGNSSchematics Evaluation Board with 50 Ohm Matching NetworkPCB Layout Top View Bottom View Si4421Frequency Dependent Component Values SchematicsSi4421 Evaluation Board with Resonant PCB Antenna BIFATop View Bottom View Si4421PCB Layout Antenna designed for 868/915 MHz band See Detail “A” Section B-B Si4421 PACKAGE INFORMATION16-pinTSSOP Related Resources RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Demo Boards and Development KitsSi4421