Silicon Laboratories SI4421 manual Data Validity Blocks, Crystal Oscillator, Wake-UpTimer, Si4421

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Data Validity Blocks

Si4421

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level. It goes high if the received signal strength exceeds a given preprogrammed level. An analog RSSI signal is also available. The RSSI settling time depends on the external filter capacitor. Pin 15 is used as analog RSSI output. The digital RSSI can be monitored by reading the status register.

Typical Analog ARSSI Voltage vs. RF Input Power

DQD

The operation of the Data Quality Detector is based on counting the spikes on the unfiltered received data. High output signal indicates an operating FSK transmitter within baseband filter bandwidth from the local oscillator. DQD threshold parameter can be set by using the Data Filter Command (page 19).

AFC

By using an integrated Automatic Frequency Control (AFC) feature, the receiver can minimize the TX/RX offset in discrete steps, allowing the use of:

∙Narrower receiver bandwidth (i.e. increased sensitivity)

∙Higher data rate

∙Inexpensive crystals

Crystal Oscillator

The Si4421 has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.

The transceiver can supply a clock signal for the microcontroller; so accurate timing is possible without the need for a second crystal.

When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Power Management Command (page 15), the chip provides a fixed number (192) of further clock pulses (“clock tail”) for the microcontroller to let it go to idle or sleep mode. If this clock output is not used, it is

suggested to turn the output buffer off by the Power Management Command (page 15).

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and generates an interrupt if it falls below a programmable threshold level. The detector circuit has 50 mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 µA typical) and can be programmed from 1 ms to several days with an accuracy of ±10%.

The wake-up timer calibrates itself to the crystal oscillator at every startup. For proper calibration of the wake-up timer the crystal oscillator must be running before the wake-up timer is enabled. The calibration process takes approximately 0.5ms. For the crystal start up time (tsx), see page 11.

Event Handling

In order to minimize current consumption, the transceiver supports different power saving modes. Active mode can be initiated by several wake-up events (negative logical pulse on nINT input, wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up or receiving a request through the serial interface).

If any wake-up event occurs, the wake-up logic generates an interrupt signal, which can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active. The source of the interrupt can be read out from the transceiver by the microcontroller through the SDO pin.

Interface and Controller

An SPI compatible serial interface lets the user select the frequency band, center frequency of the synthesizer, and the bandwidth of the baseband signal path. Division ratio for the microcontroller clock, wake-up timer period, and low supply voltage detector threshold are also programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set to default after power-on; the programmed values are retained during sleep mode. The interface supports the read-out of a status register, providing detailed information about the status of the transceiver and the received data.

The transmitter block is equipped with two 8-bit wide TX data registers. It is possible to write 8 bits into the register in burst mode and the internal bit rate generator transmits the bits out with the predefined rate. For further details, see the TX Register Buffered Data Transmission section (page 28).

It is also possible to store the received data bits into a FIFO register and read them out in a buffered mode.

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Contents TYPICAL APPLICATIONS FUNCTIONAL BLOCK DIAGRAMFEATURES DESCRIPTIONSi4421 DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Data Filtering and Clock RecoveryCrystal Oscillator Low Battery Voltage DetectorWake-UpTimer Data Validity BlocksFunction Si4421 PACKAGE PIN DEFINITIONSName TypeInternal connection Si4421Internal Pin Connections NameSi4421 PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Note These pins can be left floatingPin Function vs. Operation Mode Si4421Typical Application Recommended supply decoupling capacitor valuesSi4421 GENERAL DEVICE SPECIFICATIONS Absolute Maximum Ratings non-operatingRecommended Operating Range ELECTRICAL SPECIFICATION DC CharacteristicsSi4421 AC Characteristics PLL parameters AC Characteristics ReceiverSi4421 AC Characteristics Others Si4421AC Characteristics Transmitter AC Characteristics Turn-on/TurnaroundtimingsNote 10 By design Si4421Si4421 CONTROL INTERFACE Timing SpecificationTiming Diagram Control Commands Control Register Default ValuesSi4421 Si4421 Description of the Control CommandsConfiguration Setting Command 2. Power Management CommandSi4421 Logic connections between power control bitsSi4421 Frequency Setting Command4. Data Rate Command 5. Receiver Control CommandSi4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode CommandSi4421 8. Synchron Pattern Command9. Receiver FIFO Read Command 10. AFC CommandBit 5-4rl1 to rl0 Si442111. TX Configuration Control Command Frequency Setting CommandSi4421 13. Transmitter Register Write Command 12. PLL Setting CommandSi4421 14. Wake-UpTimer Command 15.Low Duty-CycleCommandSi4421 Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration17. Status Read Command Si4421Bit Name Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 38.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 9.6 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Si4421 Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page SW Reset CommandChannel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSSi4421 BER Curves in 433 MHz BandBER Curves in 868 MHz Band 434 MHz Si4421Frequency Dependent Component Values Si4421 REFERENCE DESIGNSSchematics Evaluation Board with 50 Ohm Matching NetworkPCB Layout Top View Bottom View Si4421Frequency Dependent Component Values SchematicsSi4421 Evaluation Board with Resonant PCB Antenna BIFASi4421 PCB Layout Antenna designed for 868/915 MHz bandTop View Bottom View Si4421 PACKAGE INFORMATION 16-pinTSSOPSee Detail “A” Section B-B Related Resources RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Demo Boards and Development KitsSi4421
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