Silicon Laboratories SI4421 manual Si4421 CRYSTAL SELECTION GUIDELINES, Bit Rate 2.4 kbps

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Si4421

Si4421

CRYSTAL SELECTION GUIDELINES

The crystal oscillator of the Si4421 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.

When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0 ) value is expected for the crystal, the oscillator is able to start up with any crystal having less than 100 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster oscillator startup.

The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore, fLO is directly proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined from the maximum allowable local oscillator frequency error.

Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0.

Maximum XTAL Tolerances Including Temperature and Aging [ppm]

Bit Rate: 2.4 kbps

				Deviation [± kHz]
	30	45	60	75		90	105	120
433 MHz	20	30	50	70		90	100	100
868 MHz	10	20	25	30		40	50	60
915 MHz	10	15	25	30		40	50	50

Bit Rate: 9.6 kbps

				Deviation [± kHz]
	30	45	60	75		90	105	120
433 MHz	15	30	50	70		80	100	100
868 MHz	8	15	25	30		40	50	60
915 MHz	8	15	25	30		40	50	50

Bit Rate: 38.4 kbps

				Deviation [± kHz]
	30	45	60	75		90	105	120
433 MHz	don't use	5	20	30		50	75	75
868 MHz	don't use	3	10	20		25	30	40
915 MHz	don't use	3	10	15		25	30	40

Bit Rate: 115.2 kbps

				Deviation [± kHz]
	105	120	135	150		165	180	195
433 MHz	don't use	3	20	30		50	70	80
868 MHz	don't use	don't use	10	20		25	35	45
915 MHz	don't use	don't use	10	15		25	30	40

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Contents FUNCTIONAL BLOCK DIAGRAM FEATURESDESCRIPTION TYPICAL APPLICATIONSDETAILED FEATURE-LEVELDESCRIPTION RF Power Amplifier PAData Filtering and Clock Recovery Si4421Low Battery Voltage Detector Wake-UpTimerData Validity Blocks Crystal OscillatorSi4421 PACKAGE PIN DEFINITIONS NameType FunctionSi4421 Internal Pin ConnectionsName Internal connectionPIN6 Logic Diagram FSK / DATA / nFFS PIN10 Logic Diagram nRES I/ONote These pins can be left floating Si4421Si4421 Typical ApplicationRecommended supply decoupling capacitor values Pin Function vs. Operation ModeRecommended Operating Range Si4421 GENERAL DEVICE SPECIFICATIONSAbsolute Maximum Ratings non-operating Si4421 ELECTRICAL SPECIFICATIONDC Characteristics Si4421 AC Characteristics PLL parametersAC Characteristics Receiver Si4421 AC Characteristics TransmitterAC Characteristics Turn-on/Turnaroundtimings AC Characteristics OthersSi4421 Note 10 By designTiming Diagram Si4421 CONTROL INTERFACETiming Specification Si4421 Control CommandsControl Register Default Values Description of the Control Commands Configuration Setting Command2. Power Management Command Si4421Logic connections between power control bits Si4421Frequency Setting Command 4. Data Rate Command5. Receiver Control Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si44218. Synchron Pattern Command 9. Receiver FIFO Read Command10. AFC Command Si4421Si4421 Bit 5-4rl1 to rl0Si4421 11. TX Configuration Control CommandFrequency Setting Command Si4421 13. Transmitter Register Write Command12. PLL Setting Command Si4421 14. Wake-UpTimer Command15.Low Duty-CycleCommand Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421Bit Name 17. Status Read CommandSi4421 Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESSi4421 CRYSTAL SELECTION GUIDELINES Bit Rate 2.4 kbpsBit Rate 9.6 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Sensitive Reset Enabled, Ripple on Vdd FIFO and Reset Mode Command pageSW Reset Command Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingBER Curves in 868 MHz Band Si4421BER Curves in 433 MHz Band Si4421 434 MHzSi4421 REFERENCE DESIGNS SchematicsEvaluation Board with 50 Ohm Matching Network Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewSchematics Si4421Evaluation Board with Resonant PCB Antenna BIFA Frequency Dependent Component ValuesTop View Bottom View Si4421PCB Layout Antenna designed for 868/915 MHz band See Detail “A” Section B-B Si4421 PACKAGE INFORMATION16-pinTSSOP RELATED PRODUCTS AND DOCUMENTS Si4421 Universal ISM Band FSK TransceiverDemo Boards and Development Kits Related ResourcesSi4421