Silicon Laboratories SI4421 manual Si4421 RESET MODES

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Si4421

Si4421

RESET MODES

The chip will enter into reset mode if any of the following conditions are met:

∙Power-on reset: During a power up sequence until the Vdd has reached the correct level and stabilized

∙Power glitch reset: Transients present on the Vdd line

∙Software reset: Special control command received by the chip

Power-on reset

After power up the supply voltage starts to rise from 0V. The reset block has an internal ramping voltage reference (reset-ramp signal), which is rising at 100mV/ms (typical) rate. The chip remains in reset state while the voltage difference between the actual Vdd and the internal reset-ramp signal is higher than the reset threshold voltage, which is 600 mV (typical). As long as the Vdd voltage is less than 1.6V (typical) the chip stays in reset mode regardless the voltage difference between the Vdd and the internal ramp signal.

The reset event can last up to 100ms supposing that the Vdd reaches 90% its final value within 1ms. During this period, the chip does not accept control commands via the serial control interface.

Power-on reset example:

Power glitch reset

The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is sensitive, which can be changed by the appropriate control command (see Related control commands at the end of this section). In normal mode the power glitch detection circuit is disabled.

There can be spikes or glitches on the Vdd line if the supply filtering is not satisfactory or the internal resistance of the power supply is too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if the positive going edge of the Vdd has a rising rate greater than 100mV/ms and the voltage difference between the internal ramp signal and the Vdd reaches the reset threshold voltage (600 mV). Typical case when the battery is weak and due to its increased internal resistance a sudden decrease of the current consumption (for example turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by one) can help to avoid this problem.

Any negative change in the supply voltage will not cause reset event unless the Vdd level reaches the reset threshold voltage (250mV in normal mode, 1.6V in sensitive reset mode).

If the sensitive mode is disabled and the power supply turned off the Vdd must drop below 250mV in order to trigger a power-on reset event when the supply voltage is turned back on. If the decoupling capacitors keep their charges for a long time it could happen that no reset will be generated upon power-up because the power glitch detector circuit is disabled.

Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.

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Contents DESCRIPTION FUNCTIONAL BLOCK DIAGRAMFEATURES TYPICAL APPLICATIONSData Filtering and Clock Recovery DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Si4421Data Validity Blocks Low Battery Voltage DetectorWake-UpTimer Crystal OscillatorType Si4421 PACKAGE PIN DEFINITIONSName FunctionName Si4421Internal Pin Connections Internal connectionNote These pins can be left floating PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Si4421Recommended supply decoupling capacitor values Si4421Typical Application Pin Function vs. Operation ModeAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 AC Characteristics Turn-on/Turnaroundtimings Si4421AC Characteristics Transmitter AC Characteristics OthersSi4421 Note 10 By designTiming Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 2. Power Management Command Description of the Control CommandsConfiguration Setting Command Si4421Logic connections between power control bits Si44215. Receiver Control Command Frequency Setting Command4. Data Rate Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si442110. AFC Command 8. Synchron Pattern Command9. Receiver FIFO Read Command Si4421Si4421 Bit 5-4rl1 to rl0Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421Si4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESBit Rate 9.6 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES SW Reset Command Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band Si4421 434 MHzEvaluation Board with 50 Ohm Matching Network Si4421 REFERENCE DESIGNSSchematics Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewEvaluation Board with Resonant PCB Antenna BIFA SchematicsSi4421 Frequency Dependent Component ValuesPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B Demo Boards and Development Kits RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Related ResourcesSi4421
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