Silicon Laboratories SI4421 manual Si4421 PACKAGE PIN DEFINITIONS, Name, Type, Function

Page 4
Si4421

Si4421

PACKAGE PIN DEFINITIONS

Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output

Pin

 

 

Name

 

Type

 

Function

1

 

 

SDI

 

DI

 

Data input of the serial control interface

2

 

 

SCK

 

DI

 

Clock input of the serial control interface

3

 

 

nSEL

 

DI

 

Chip select input of the serial control interface (active low)

4

 

 

SDO

 

DO

 

Serial data output with bus hold

5

 

 

nIRQ

 

DO

 

Interrupt request output (active low)

 

 

 

FSK

 

DI

 

Transmit FSK data input (internal pull up resistor 133 k)

6

 

 

DATA

 

DO

 

Received data output (FIFO not used)

 

 

 

nFFS

 

DI

 

FIFO select input (active low). In FIFO mode, when bit ef is set in Configuration Setting Command,

 

 

 

 

 

page 15 (internal pull up resistor 133 k)

 

 

 

 

 

 

 

 

 

 

DLCK

 

DO

 

Received data clock output (Digital filter used, FIFO not used)

7

 

 

CFIL

 

AIO

 

External data filter capacitor connection (Analog filter used)

 

 

 

FFIT

 

DO

 

FIFO interrupt (active high). In FIFO mode, when bit ef is set in Configuration Setting Command

8

 

 

CLK

 

DO

 

Microcontroller clock output

9

 

 

XTL

 

AIO

 

Crystal connection (the other terminal of crystal to VSS) or external reference input

 

 

REF

 

AIO

 

External reference input. Use 33 pF series coupling capacitor

 

 

 

 

 

10

 

 

nRES

 

DIO

 

Open drain reset output with internal pull-up and input buffer (active low)

11

 

 

VSS

 

S

Ground reference voltage

12

 

 

RF2

 

AIO

 

RF differential signal input/output

13

 

 

RF1

 

AIO

 

RF differential signal input/output

14

 

 

VDD

 

S

 

Positive supply voltage

15

 

 

ARSSI

 

AO

 

Analog RSSI output

16

 

 

nINT

 

DI

 

Interrupt input (active low)

 

 

VDI

 

DO

 

Valid data indicator output

 

 

 

 

 

Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.

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Image 4
Contents FUNCTIONAL BLOCK DIAGRAM FEATURESDESCRIPTION TYPICAL APPLICATIONSDETAILED FEATURE-LEVELDESCRIPTION RF Power Amplifier PAData Filtering and Clock Recovery Si4421Low Battery Voltage Detector Wake-UpTimerData Validity Blocks Crystal OscillatorSi4421 PACKAGE PIN DEFINITIONS NameType FunctionSi4421 Internal Pin ConnectionsName Internal connectionPIN6 Logic Diagram FSK / DATA / nFFS PIN10 Logic Diagram nRES I/ONote These pins can be left floating Si4421Si4421 Typical ApplicationRecommended supply decoupling capacitor values Pin Function vs. Operation ModeAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 Si4421 AC Characteristics TransmitterAC Characteristics Turn-on/Turnaroundtimings AC Characteristics OthersSi4421 Note 10 By designTiming Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 Description of the Control Commands Configuration Setting Command2. Power Management Command Si4421Logic connections between power control bits Si4421Frequency Setting Command 4. Data Rate Command5. Receiver Control Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si44218. Synchron Pattern Command 9. Receiver FIFO Read Command10. AFC Command Si4421Si4421 Bit 5-4rl1 to rl0Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421Si4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESSi4421 CRYSTAL SELECTION GUIDELINES Bit Rate 2.4 kbpsBit Rate 9.6 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Sensitive Reset Enabled, Ripple on Vdd FIFO and Reset Mode Command pageSW Reset Command Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band Si4421 434 MHzSi4421 REFERENCE DESIGNS SchematicsEvaluation Board with 50 Ohm Matching Network Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewSchematics Si4421Evaluation Board with Resonant PCB Antenna BIFA Frequency Dependent Component ValuesPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B RELATED PRODUCTS AND DOCUMENTS Si4421 Universal ISM Band FSK TransceiverDemo Boards and Development Kits Related ResourcesSi4421