Silicon Laboratories SI4421 manual Si4421 CONTROL INTERFACE, Timing Specification, Timing Diagram

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Si4421

Si4421

CONTROL INTERFACE

Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16- bit command). Bits having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built- in hardware serial port is used. If the port cannot be switched to 16-bit mode then a separate I/O line should be used to control the nSEL pin to ensure the low level during the whole duration of the command or a software serial control interface should be implemented. The Power-On Reset (POR) circuit sets default values in all control and command registers.

The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:

∙The TX register is ready to receive the next byte (RGIT)

∙The RX FIFO has received the preprogrammed amount of bits (FFIT)

∙Power-on reset (POR)

∙RX FIFO overflow (FFOV) / TX register underrun (RGUR)

∙Wake-up timer timeout (WKUP)

∙Negative pulse on the interrupt input pin nINT (EXT)

∙Supply voltage below the preprogrammed value is detected (LBD)

FFIT and FFOV are applicable when the RX FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out.

Timing Specification

Symbol	Parameter	Minimum value [ns]
tCH	Clock high time	25
tCL	Clock low time	25
tSS	Select setup time (nSEL falling edge to SCK rising edge)	10
tSH	Select hold time (SCK falling edge to nSEL rising edge)	10
tSHI	Select high time	25
tDS	Data setup time (SDI transition to SCK rising edge)	5
tDH	Data hold time (SCK rising edge to SDI transition)	5
tOD	Data delay time	10

Timing Diagram

t							tSHI
SS
nSEL
	tCH	tCL			tOD		tSH
SCK
tDS	tDH
SDI	BIT15	BIT14	BIT13	BIT8	BIT7	BIT1	BIT0
SDO	FFIT	FFOV		CRL	ATS	OFFS(0)	FIFOOUT

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Contents FEATURES FUNCTIONAL BLOCK DIAGRAMDESCRIPTION TYPICAL APPLICATIONSRF Power Amplifier PA DETAILED FEATURE-LEVELDESCRIPTIONData Filtering and Clock Recovery Si4421Wake-UpTimer Low Battery Voltage DetectorData Validity Blocks Crystal OscillatorName Si4421 PACKAGE PIN DEFINITIONSType FunctionInternal Pin Connections Si4421Name Internal connectionPIN10 Logic Diagram nRES I/O PIN6 Logic Diagram FSK / DATA / nFFSNote These pins can be left floating Si4421Typical Application Si4421Recommended supply decoupling capacitor values Pin Function vs. Operation ModeAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 AC Characteristics Transmitter Si4421AC Characteristics Turn-on/Turnaroundtimings AC Characteristics OthersNote 10 By design Si4421Timing Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 Configuration Setting Command Description of the Control Commands2. Power Management Command Si4421Si4421 Logic connections between power control bits4. Data Rate Command Frequency Setting Command5. Receiver Control Command Si4421Si4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode Command9. Receiver FIFO Read Command 8. Synchron Pattern Command10. AFC Command Si4421Bit 5-4rl1 to rl0 Si4421Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configurationSi4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 2.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 9.6 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES FIFO and Reset Mode Command page Sensitive Reset Enabled, Ripple on VddSW Reset Command Si4421Channel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band 434 MHz Si4421Schematics Si4421 REFERENCE DESIGNSEvaluation Board with 50 Ohm Matching Network Frequency Dependent Component ValuesPCB Layout Top View Bottom View Si4421Si4421 SchematicsEvaluation Board with Resonant PCB Antenna BIFA Frequency Dependent Component ValuesPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B Si4421 Universal ISM Band FSK Transceiver RELATED PRODUCTS AND DOCUMENTSDemo Boards and Development Kits Related ResourcesSi4421