Silicon Laboratories SI4421 manual Description, Functional Block Diagram, Features, Si4421

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Si4421 Universal ISM Band FSK Transceiver

Si4421 Universal ISM Band FSK Transceiver

DESCRIPTION

Silicon Labs’ Si4421 is a single chip, low power, multi-channel FSK transceiver designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the 433, 868 and 915 MHz bands. The Si4421 transceiver is a part of Silicon Labs’ EZRadioTM product line, which produces a flexible, low cost, and highly integrated solution that does not require production alignments. The chip is a complete analog RF and baseband transceiver including a multi-band PLL synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and amplifiers, and an I/Q demodulator. All required RF functions are integrated. Only an external crystal and bypass filtering are needed for operation.

The Si4421 features a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLL’s high resolution allows the usage of multiple channels in any of the bands. The receiver baseband bandwidth (BW) is programmable to accommodate various deviation, data rate and crystal tolerance requirements. The transceiver employs the Zero-IF approach with I/Q demodulation. Consequently, no external components (except crystal and decoupling) are needed in most applications.

The Si4421 dramatically reduces the load on the microcontroller with the integrated digital data processing features: data filtering, clock recovery, data pattern recognition, integrated FIFO and TX data register. The automatic frequency control (AFC) feature allows the use of a low accuracy (low cost) crystal. To minimize the system cost, the Si4421 can provide a clock signal for the microcontroller, avoiding the need for two crystals.

For low power applications, the Si4421 supports low duty cycle operation based on the internal wake-up timer.

FUNCTIONAL BLOCK DIAGRAM

 

 

MIX

I

AMP

OC

 

 

 

 

7

DCLK /

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CFIL /

RF1

13

 

 

 

 

I/Q

 

Data Filt

clk

 

FFIT /

 

LNA

 

 

 

Self cal.

 

data

 

FSK /

RF2

 

 

 

DEMOD

 

CLK Rec

6

12

MIX

 

 

 

 

 

 

 

 

DATA /

 

 

Q

 

 

 

 

 

 

 

nFFS

 

 

 

AMP

OC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PA

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLL & I/Q VCO

 

 

RSSI

COMP

DQD

AFC

 

 

 

 

 

with cal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RF Parts

 

BB Amp/Filt./Limiter

 

 

Data processing units

 

 

 

CLK div

Xosc

WTM

 

LBD

 

Controller

 

Bias

 

 

 

with cal.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low Power parts

 

 

 

 

 

 

8

9

15

1

2

3

4

5

10

16

11

14

CLK

XTL /

ARSSI SDI SCK nSEL SDO nIRQ nRES nINT /

VSS VDD

 

REF

VDI

 

Si4421

PIN ASSIGNMENT

This document refers to Si4421-IC rev A1.

See www.silabs.com/integration for any applicable errata.

See back page for ordering information.

FEATURES

Fully integrated (low BOM, easy design-in)

No alignment required in production

Fast-settling, programmable, high-resolution PLL synthesizer

Fast frequency-hopping capability

High bit rate (up to 115.2 kbps in digital mode and 256 kbps in analog mode)

Direct differential antenna input/output

Integrated power amplifier

Programmable TX frequency deviation (15 to 240 kHz)

Programmable RX baseband bandwidth (67 to 400 kHz)

Analog and digital RSSI outputs

Automatic frequency control (AFC)

Data quality detection (DQD)

Internal data filtering and clock recovery

RX synchron pattern recognition

SPI compatible serial control interface

Clock and reset signals for microcontroller

16-bit RX Data FIFO

Two 8-bit TX data registers

Low power duty cycle mode

Standard 10 MHz crystal reference with on-chip tuning

Wake-up timer

2.2 to 3.8 V supply voltage

Low power consumption

Low standby current (0.3 μA)

Compact 16 pin TSSOP package

Supports very short packets (down to 3 bytes)

Excellent temperature stability of the RF parameters

Good adjacent channel rejection/blocking

TYPICAL APPLICATIONS

Home security and alarm

Remote control, keyless entry

Wireless keyboard/mouse and other PC peripherals

Toy controls

Remote keyless entry

Tire pressure monitoring

Telemetry

Personal/patient data logging

Remote automatic meter reading

 

 

 

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Si4421-DS rev 2.4r 0708

www.silabs.com

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Contents FEATURES FUNCTIONAL BLOCK DIAGRAMDESCRIPTION TYPICAL APPLICATIONSRF Power Amplifier PA DETAILED FEATURE-LEVELDESCRIPTIONData Filtering and Clock Recovery Si4421Wake-UpTimer Low Battery Voltage DetectorData Validity Blocks Crystal OscillatorName Si4421 PACKAGE PIN DEFINITIONSType FunctionInternal Pin Connections Si4421Name Internal connectionPIN10 Logic Diagram nRES I/O PIN6 Logic Diagram FSK / DATA / nFFSNote These pins can be left floating Si4421Typical Application Si4421Recommended supply decoupling capacitor values Pin Function vs. Operation ModeAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 AC Characteristics Transmitter Si4421AC Characteristics Turn-on/Turnaroundtimings AC Characteristics OthersNote 10 By design Si4421Timing Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 Configuration Setting Command Description of the Control Commands2. Power Management Command Si4421Si4421 Logic connections between power control bits4. Data Rate Command Frequency Setting Command5. Receiver Control Command Si4421Si4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode Command9. Receiver FIFO Read Command 8. Synchron Pattern Command10. AFC Command Si4421Bit 5-4rl1 to rl0 Si4421Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configurationSi4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 2.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 9.6 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES FIFO and Reset Mode Command page Sensitive Reset Enabled, Ripple on VddSW Reset Command Si4421Channel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band 434 MHz Si4421Schematics Si4421 REFERENCE DESIGNSEvaluation Board with 50 Ohm Matching Network Frequency Dependent Component ValuesPCB Layout Top View Bottom View Si4421Si4421 SchematicsEvaluation Board with Resonant PCB Antenna BIFA Frequency Dependent Component ValuesPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B Si4421 Universal ISM Band FSK Transceiver RELATED PRODUCTS AND DOCUMENTSDemo Boards and Development Kits Related ResourcesSi4421