Silicon Laboratories SI4421 manual Si4421, Typical TX register usage

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Typical TX register usage

Si4421

Typical TX register usage

Enabling the Transmitter preloads the TX

latch with 0xAAAA

Do not switch the et off here, because the

TX byte1 is not transmitted out only stored into the internal register!

SPI commands

Conf. Set.

Power Man

 

TX latch wr

TX latch wr

Power Man

Conf. Set.

(nSEL, SCK, SDI)

el = 1

et = 1

 

TX byte1

Dummy

et = 0

el = 0

 

 

 

 

TX byte

 

 

 

 

 

 

 

et bit

 

 

 

 

 

 

 

(enable transmitter)

 

 

 

 

 

 

 

enable

 

Synt.

PA

 

 

 

 

Synthesizer / PA

 

 

 

 

 

 

Ttx_XTAL_ON*

 

 

 

 

 

 

 

 

 

 

 

 

TX data

 

 

0xAA

0xAA

TX byte1

 

 

 

 

 

 

 

 

Fraction of the

 

 

 

 

 

 

Dummy byte

nIRQ

SDO**

Notes:

*Ttx_XTAL_ON is the start-up time of the PLL + PA with running crystal oscillator ** SDO is tri-state if nSEL is logic high.

Note: The content of the data registers are initialized by clearing bit et.

A complete transmit sequence should be performed as follows:

a.Enable the TX register by setting the el bit to 1 (Configuration Setting Command, page 15)

b.The TX register automatically filled out with 0xAAAA, which can be used to generate preamble.

c.Enable the transmitter by setting the et bit (Power Management Command, page 15)

d.The synthesizer and the PLL turns on, calibrates itself then the power amplifier automatically enabled

e.The TX data transmission starts

f.When the transmission of the byte completed, the nIRQ pin goes high, the SDO pin goes low at the same time. The nIRQ pulse shows that the first 8 bits (the first byte, by default 0xAA) has transmitted. There are still 8 bits in the transmit register.

g.The microcontroller recognizes the interrupt and writes a data byte to the TX register

h.Repeat f. - g. until the last data byte reached

i.Using the same method, transmit a dummy byte. The value of this dummy byte can be anything.

j.The next high to low transition on the nIRQ line (or low to high on the SDO pin) shows that the transmission of the data bytes ended. The dummy byte is still in the TX latch.

k.Turn off the transmitter by setting the et bit to 0. This event will probably happen while the dummy byte is being transmitted. Since the dummy byte contains no useful information, this corruption will cause no problems.

l.Clearing the el bit clears the Register Underrun interrupt; the nIRQ pin goes high, the SDO low.

It is possible to perform this sequence without sending a dummy byte (step i.) but after loading the last data byte to the transmit register the PA turn off should be delayed for at least 16 bits time. The clock source of the microcontroller (if the clock is not supplied by the Si4421) should be stable enough over temperature and voltage to ensure this minimum delay under all operating circumstances.

When the dummy byte is used, the whole process is driven by interrupts. Changing the TX data rate has no effect on the algorithm and no accurate delay measurement is needed.

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Contents DESCRIPTION FUNCTIONAL BLOCK DIAGRAMFEATURES TYPICAL APPLICATIONSData Filtering and Clock Recovery DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Si4421Data Validity Blocks Low Battery Voltage DetectorWake-UpTimer Crystal OscillatorType Si4421 PACKAGE PIN DEFINITIONSName FunctionName Si4421Internal Pin Connections Internal connectionNote These pins can be left floating PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Si4421Recommended supply decoupling capacitor values Si4421Typical Application Pin Function vs. Operation ModeSi4421 GENERAL DEVICE SPECIFICATIONS Absolute Maximum Ratings non-operatingRecommended Operating Range ELECTRICAL SPECIFICATION DC CharacteristicsSi4421 AC Characteristics PLL parameters AC Characteristics ReceiverSi4421 AC Characteristics Turn-on/Turnaroundtimings Si4421AC Characteristics Transmitter AC Characteristics OthersSi4421 Note 10 By designSi4421 CONTROL INTERFACE Timing SpecificationTiming Diagram Control Commands Control Register Default ValuesSi4421 2. Power Management Command Description of the Control CommandsConfiguration Setting Command Si4421Logic connections between power control bits Si44215. Receiver Control Command Frequency Setting Command4. Data Rate Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si442110. AFC Command 8. Synchron Pattern Command9. Receiver FIFO Read Command Si4421Si4421 Bit 5-4rl1 to rl011. TX Configuration Control Command Frequency Setting CommandSi4421 13. Transmitter Register Write Command 12. PLL Setting CommandSi4421 14. Wake-UpTimer Command 15.Low Duty-CycleCommandSi4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421 17. Status Read Command Si4421 Bit Name Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESBit Rate 9.6 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES SW Reset Command Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingSi4421 BER Curves in 433 MHz BandBER Curves in 868 MHz Band Si4421 434 MHzEvaluation Board with 50 Ohm Matching Network Si4421 REFERENCE DESIGNSSchematics Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewEvaluation Board with Resonant PCB Antenna BIFA SchematicsSi4421 Frequency Dependent Component ValuesSi4421 PCB Layout Antenna designed for 868/915 MHz bandTop View Bottom View Si4421 PACKAGE INFORMATION 16-pinTSSOPSee Detail “A” Section B-B Demo Boards and Development Kits RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Related ResourcesSi4421
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