Silicon Laboratories SI4421 Si4421 RX FIFO BUFFERED DATA READ, Recommended Packet Structures

Contents TYPICAL APPLICATIONS FUNCTIONAL BLOCK DIAGRAMFEATURES DESCRIPTIONSi4421 DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Data Filtering and Clock RecoveryCrystal Oscillator Low Battery Voltage DetectorWake-UpTimer Data Validity BlocksFunction Si4421 PACKAGE PIN DEFINITIONSName TypeInternal connection Si4421Internal Pin Connections NameSi4421 PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Note These pins can be left floatingPin Function vs. Operation Mode Si4421Typical Application Recommended supply decoupling capacitor valuesAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 AC Characteristics Others Si4421AC Characteristics Transmitter AC Characteristics Turn-on/TurnaroundtimingsNote 10 By design Si4421Timing Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 Si4421 Description of the Control CommandsConfiguration Setting Command 2. Power Management CommandSi4421 Logic connections between power control bitsSi4421 Frequency Setting Command4. Data Rate Command 5. Receiver Control CommandSi4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode CommandSi4421 8. Synchron Pattern Command9. Receiver FIFO Read Command 10. AFC CommandBit 5-4rl1 to rl0 Si4421Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configurationSi4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 38.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 9.6 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Si4421 Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page SW Reset CommandChannel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band 434 MHz Si4421Frequency Dependent Component Values Si4421 REFERENCE DESIGNSSchematics Evaluation Board with 50 Ohm Matching NetworkPCB Layout Top View Bottom View Si4421Frequency Dependent Component Values SchematicsSi4421 Evaluation Board with Resonant PCB Antenna BIFAPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B Related Resources RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Demo Boards and Development KitsSi4421