Silicon Laboratories SI4421 manual Si4421, Bit 5-4rl1 to rl0

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Bit 5-4 (rl1 to rl0):

Si4421

Bit 5-4 (rl1 to rl0):			Range limit. Limits the value of the frequency offset register to the next values:

	rl1		rl0			Max deviation		fres:
	0		0			No restriction		433 MHz bands: 2.5 kHz
	0		1			+15 fres to -16 fres		868 MHz band: 5 kHz
	1		0			+7 fres to -8 fres		868 MHz band: 5 kHz
	1		0			+7 fres to -8 fres		915 MHz band: 7.5 kHz
	1		1			+3 fres to -4 fres		915 MHz band: 7.5 kHz
	1		1			+3 fres to -4 fres
Bit 3 (st):	Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of
	the AFC block.
Bit 2 (fi):	Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice as long, but the
	measurement uncertainty is about half.
Bit 1 (oe):	Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of
	the PLL.

Bit 0 (en):

Enables the calculation of the offset frequency by the AFC circuit.

In manual mode, the strobe signal is provided by the microcontroller. One measurement cycle (and strobe) signal can compensate about 50-60% of the actual frequency offset. Two measurement cycles can compensate 80%, and three measurement cycles can compensate 92%. The ATGL bit in the status register can be used to determine when the actual measurement cycle is finished.

In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the same result in two subsequent cycles.

Without AFC the transmitter and the receiver needs to be tuned precisely to the same frequency. RX/TX frequency offset can lower the range. The units must be adjusted carefully during production, stable, expensive crystal must be used to avoid drift or the output power needs to be increased to compensate yield loss.

The AFC block will calculate the TX-RX offset. This value will be used to pull the RX synthesizer close to the frequency of the transmitter. The main benefits of the automatic frequency control: cheap crystal can be used, the temperature or aging drift will not cause range loss and no production alignment needed.

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Contents DESCRIPTION FUNCTIONAL BLOCK DIAGRAMFEATURES TYPICAL APPLICATIONSData Filtering and Clock Recovery DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Si4421Data Validity Blocks Low Battery Voltage DetectorWake-UpTimer Crystal OscillatorType Si4421 PACKAGE PIN DEFINITIONSName FunctionName Si4421Internal Pin Connections Internal connectionNote These pins can be left floating PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Si4421Recommended supply decoupling capacitor values Si4421Typical Application Pin Function vs. Operation ModeAbsolute Maximum Ratings non-operating Si4421 GENERAL DEVICE SPECIFICATIONSRecommended Operating Range DC Characteristics ELECTRICAL SPECIFICATIONSi4421 AC Characteristics Receiver AC Characteristics PLL parametersSi4421 AC Characteristics Turn-on/Turnaroundtimings Si4421AC Characteristics Transmitter AC Characteristics OthersSi4421 Note 10 By designTiming Specification Si4421 CONTROL INTERFACETiming Diagram Control Register Default Values Control CommandsSi4421 2. Power Management Command Description of the Control CommandsConfiguration Setting Command Si4421Logic connections between power control bits Si44215. Receiver Control Command Frequency Setting Command4. Data Rate Command Si4421VDI Logic Diagram Si44216. Data Filter Command Si44217.FIFO and Reset Mode Command Si442110. AFC Command 8. Synchron Pattern Command9. Receiver FIFO Read Command Si4421Si4421 Bit 5-4rl1 to rl0Frequency Setting Command 11. TX Configuration Control CommandSi4421 12. PLL Setting Command 13. Transmitter Register Write CommandSi4421 15.Low Duty-CycleCommand 14. Wake-UpTimer CommandSi4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration Si4421Si4421 17. Status Read CommandBit Name Si4421 INTERRUPT HANDLING TX REGISTER BUFFERED DATA TRANSMISSION Si4421Si4421 Typical TX register usageSi4421 RX FIFO BUFFERED DATA READ RECOMMENDED PACKET STRUCTURESBit Rate 9.6 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES SW Reset Command Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page Si4421Si4421 TYPICAL PERFORMANCE CHARACTERISTICS Channel Selectivity and BlockingBER Curves in 433 MHz Band Si4421BER Curves in 868 MHz Band Si4421 434 MHzEvaluation Board with 50 Ohm Matching Network Si4421 REFERENCE DESIGNSSchematics Frequency Dependent Component ValuesSi4421 PCB Layout Top View Bottom ViewEvaluation Board with Resonant PCB Antenna BIFA SchematicsSi4421 Frequency Dependent Component ValuesPCB Layout Antenna designed for 868/915 MHz band Si4421Top View Bottom View 16-pinTSSOP Si4421 PACKAGE INFORMATIONSee Detail “A” Section B-B Demo Boards and Development Kits RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Related ResourcesSi4421