Silicon Laboratories SI4421 manual Si4421, Status Read Command, Bit Name

Page 27
17. Status Read Command

Si4421

17. Status Read Command

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0000h

The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits will be clocked out on the SDO pin as follows:

Status Register Read Sequence with FIFO Read Example:

Bit Name

Function

RGIT

TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command, page 24)

FFIT

The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the

FIFO read methods)

 

POR

Power-on reset (Cleared after Status Read Command)

RGUR

TX register under run, register over write (Cleared after Status Read Command)

FFOV

RX FIFO overflow (Cleared after Status Read Command)

WKUP

Wake-up timer overflow (Cleared after Status Read Command)

EXT

Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command)

LBD

Low battery detect, the power supply voltage is below the pre-programmed limit

FFEM

FIFO is empty

ATS

Antenna tuning circuit detected strong enough RF signal

RSSI

The strength of the incoming signal is above the pre-programmed limit

DQD

Data quality detector output

CRL

Clock recovery locked

ATGL

Toggling in each AFC cycle

OFFS(6)

MSB of the measured frequency offset (sign of the offset value)

OFFS(3) -OFFS(0)

Offset value to be added to the value of the frequency control parameter (Four LSB bits)

Note: In order to get accurate values the AFC has to be disabled during the read by clearing the en bit in the AFC Control Command (page 21). The AFC offset value (OFFS bits in the status word) is represented as a two’s complement number. The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step (see the Frequency Setting Command on page 17).

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Image 27
Contents TYPICAL APPLICATIONS FUNCTIONAL BLOCK DIAGRAMFEATURES DESCRIPTIONSi4421 DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Data Filtering and Clock RecoveryCrystal Oscillator Low Battery Voltage DetectorWake-UpTimer Data Validity BlocksFunction Si4421 PACKAGE PIN DEFINITIONSName TypeInternal connection Si4421Internal Pin Connections NameSi4421 PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Note These pins can be left floatingPin Function vs. Operation Mode Si4421Typical Application Recommended supply decoupling capacitor valuesSi4421 GENERAL DEVICE SPECIFICATIONS Absolute Maximum Ratings non-operatingRecommended Operating Range ELECTRICAL SPECIFICATION DC CharacteristicsSi4421 AC Characteristics PLL parameters AC Characteristics ReceiverSi4421 AC Characteristics Others Si4421AC Characteristics Transmitter AC Characteristics Turn-on/TurnaroundtimingsNote 10 By design Si4421Si4421 CONTROL INTERFACE Timing SpecificationTiming Diagram Control Commands Control Register Default ValuesSi4421 Si4421 Description of the Control CommandsConfiguration Setting Command 2. Power Management CommandSi4421 Logic connections between power control bitsSi4421 Frequency Setting Command4. Data Rate Command 5. Receiver Control CommandSi4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode CommandSi4421 8. Synchron Pattern Command9. Receiver FIFO Read Command 10. AFC CommandBit 5-4rl1 to rl0 Si442111. TX Configuration Control Command Frequency Setting CommandSi4421 13. Transmitter Register Write Command 12. PLL Setting CommandSi4421 14. Wake-UpTimer Command 15.Low Duty-CycleCommandSi4421 Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration17. Status Read Command Si4421Bit Name Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 38.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 9.6 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Si4421 Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page SW Reset CommandChannel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSSi4421 BER Curves in 433 MHz BandBER Curves in 868 MHz Band 434 MHz Si4421Frequency Dependent Component Values Si4421 REFERENCE DESIGNSSchematics Evaluation Board with 50 Ohm Matching NetworkPCB Layout Top View Bottom View Si4421Frequency Dependent Component Values SchematicsSi4421 Evaluation Board with Resonant PCB Antenna BIFASi4421 PCB Layout Antenna designed for 868/915 MHz bandTop View Bottom View Si4421 PACKAGE INFORMATION 16-pinTSSOPSee Detail “A” Section B-B Related Resources RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Demo Boards and Development KitsSi4421