Silicon Laboratories SI4421 manual Tx Register Buffered Data Transmission, Si4421

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TX REGISTER BUFFERED DATA TRANSMISSION

Si4421

The best practice in interrupt handling is to start with a status read when interrupt occurs, and then make a decision based on the status byte. It is very important to mention that any interrupt can “wake-up” the EZradio chip from sleep mode. This means that the crystal oscillator starts to supply clock signal to the microcontroller even if the microcontroller has its own clock source. Also, the Si4421 will not go to low current sleep mode if any interrupt remains active regardless to the state of the ex (enable crystal oscillator) bit in the Power Management Command (page 15). This way the microcontroller always can have clock signal to process the interrupt. To prevent high current consumption and this way short battery life, it is strongly advised to process and clear every interrupt before going to sleep mode. All unnecessary functions should be turned off to avoid unwanted interrupts. Before freezing the microcontroller code, a thorough testing must be performed in order to make sure that all interrupt sources are handled before putting the radio device to low power consumption sleep mode. If the dc bit is set in the Power Management Command, then only the ex bit controls the crystal oscillator (supposing that both the er and et bits are cleared), the interrupts have no effect on it.

TX REGISTER BUFFERED DATA TRANSMISSION

In this operating mode (enabled by bit el, in the Configuration Setting Command, page 15) the TX data is clocked into one of the two 8-bit data registers. The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management Command (page 15). The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.

TX register simplified block diagram (before transmit)

TX register simplified block diagram (during transmit)

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Contents FEATURES FUNCTIONAL BLOCK DIAGRAMDESCRIPTION TYPICAL APPLICATIONSRF Power Amplifier PA DETAILED FEATURE-LEVELDESCRIPTIONData Filtering and Clock Recovery Si4421Wake-UpTimer Low Battery Voltage DetectorData Validity Blocks Crystal OscillatorName Si4421 PACKAGE PIN DEFINITIONSType FunctionInternal Pin Connections Si4421Name Internal connectionPIN10 Logic Diagram nRES I/O PIN6 Logic Diagram FSK / DATA / nFFSNote These pins can be left floating Si4421Typical Application Si4421Recommended supply decoupling capacitor values Pin Function vs. Operation ModeRecommended Operating Range Si4421 GENERAL DEVICE SPECIFICATIONSAbsolute Maximum Ratings non-operating Si4421 ELECTRICAL SPECIFICATIONDC Characteristics Si4421 AC Characteristics PLL parametersAC Characteristics Receiver AC Characteristics Transmitter Si4421AC Characteristics Turn-on/Turnaroundtimings AC Characteristics OthersNote 10 By design Si4421Timing Diagram Si4421 CONTROL INTERFACETiming Specification Si4421 Control CommandsControl Register Default Values Configuration Setting Command Description of the Control Commands2. Power Management Command Si4421Si4421 Logic connections between power control bits4. Data Rate Command Frequency Setting Command5. Receiver Control Command Si4421Si4421 VDI Logic DiagramSi4421 6. Data Filter CommandSi4421 7.FIFO and Reset Mode Command9. Receiver FIFO Read Command 8. Synchron Pattern Command10. AFC Command Si4421Bit 5-4rl1 to rl0 Si4421Si4421 11. TX Configuration Control CommandFrequency Setting Command Si4421 13. Transmitter Register Write Command12. PLL Setting Command Si4421 14. Wake-UpTimer Command15.Low Duty-CycleCommand Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configurationBit Name 17. Status Read CommandSi4421 Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSIONTypical TX register usage Si4421RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READBit Rate 2.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 9.6 kbps Bit Rate 38.4 kbpsSi4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES FIFO and Reset Mode Command page Sensitive Reset Enabled, Ripple on VddSW Reset Command Si4421Channel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICSBER Curves in 868 MHz Band Si4421BER Curves in 433 MHz Band 434 MHz Si4421Schematics Si4421 REFERENCE DESIGNSEvaluation Board with 50 Ohm Matching Network Frequency Dependent Component ValuesPCB Layout Top View Bottom View Si4421Si4421 SchematicsEvaluation Board with Resonant PCB Antenna BIFA Frequency Dependent Component ValuesTop View Bottom View Si4421PCB Layout Antenna designed for 868/915 MHz band See Detail “A” Section B-B Si4421 PACKAGE INFORMATION16-pinTSSOP Si4421 Universal ISM Band FSK Transceiver RELATED PRODUCTS AND DOCUMENTSDemo Boards and Development Kits Related ResourcesSi4421