Texas Instruments TMS320C6722, TMS320C6727 Allowed PLL Operating Conditions, Board, Emi, Pllhv

Page 103

		TMS320C6727, TMS320C6726, TMS320C6722
	www.ti.com	Floating-Point Digital Signal Processors
	www.ti.com		SPRS268E –MAY 2005 –REVISED JANUARY 2007
			SPRS268E –MAY 2005 –REVISED JANUARY 2007
	Table 4-40. Allowed PLL Operating Conditions
	PARAMETER	DEFAULT VALUE	ALLOWED SETTING OR RANGE
	PARAMETER	DEFAULT VALUE	MIN	MAX
			MIN	MAX
1	PLLRST = 1 assertion time during initialization	N/A	125 ns
2	Lock time before setting PLLEN = 1. After changing D0, PLLM, or	N/A	187.5 µs
	input clock.
3	PLL input frequency (PLLREF after D0(1))		12 MHz	50 MHz
4	PLL multiplier values (PLLM)	x13	x4	x25
5	PLL output frequency (PLLOUT before dividers D1, D2, D3)(2)	N/A	140 MHz	600 MHz
6	SYSCLK1 frequency (set by PLLM and dividers D0, D1)	PLLOUT/1		Device Frequency
				Specification
7	SYSCLK2 frequency (set by PLLM and dividers D0, D2)	PLLOUT/2	/2, /3, or /4 of SYSCLK1
8	SYSCLK3 frequency (set by PLLM and dividers D0, D3)	PLLOUT/3		EMIF Frequency
				Specification

(1)Some values for the D0 divider produce results outside of this range and should not be selected.

(2)In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.

CAUTION

SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0] to '1';and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and D3 are changed in order to make sure the change takes effect and preserves alignment.

CAUTION

When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3 dividers, the bridge BR2 in Figure 2-4must be reset by the CFGBRIDGE register. See Table 2-7.

The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V power pin (PLLHV) that should be connected to DVDD at the board level through an external filter, as illustrated in Figure 4-44.

BOARD

DVDD (3.3 V)

Place Filter and Capacitors as Close

to DSP as Possible

EMI

Filter

10mF

+

0.1mF

PLLHV

EMI Filter: TDK ACF451832−333, −223, −153, or −103,

Panasonic EXCCET103U, or Equivalent

Figure 4-44. PLL Power Supply Filter

Submit Documentation Feedback

Peripheral and Electrical Specifications

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Contents TMS320C6727, TMS320C6726, TMS320C6722 DSPs FeaturesDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics ContentsC6726 Device CharacteristicsCharacteristics of the C672x Processors Hardware FeaturesCPU Data Paths Enhanced C67x+ CPUInstruction FLOATING-POINT Improves Operation CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsByte Bank Internal Program/Data ROM and RAMRegister Name Byte Address Description Cache ModeProgram Cache Program Cache Control RegistersBlock Diagram of Crossbar Switch High-Performance Crossbar SwitchLabel Bridge Description Master Clock Target Clock Bus BridgesCsprst BIT no Name Reset Value Read Write DescriptionC672x Memory Map Memory Map SummaryFfff SPI0SIMO SPI0CLK Boot ModesRequired Boot Pin Settings at Device Reset Boot Mode UhpihcsPINCAP7 BIT no Name DescriptionPINCAP15 Pin Maps Pin AssignmentsPin Low-Profile Quad Flatpack RFP Suffix-Top View ZDH Signal Name RFP GDHTerminal Functions 12. Terminal FunctionsIO/I IPD Description ZDH AHCLKX0/AHCLKX2 AHCLKR0/AHCLKR1ACLKR0 AFSR0Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH PackageDevelopment Support DevelopmentDevice Support Package Type ‡ § TMS 320 C6727 GDH a 250Prefix Device Speed Range Device FamilyDocumentation Support C672x devices are documented in the tools v6.0 documentation Peripheral Pin Multiplexing Options Device Configuration RegistersDevice-Level Configuration Registers Options for Configuring SPI0, I2C0, and I2C1Peripheral Pin Multiplexing Control Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Configuration Option PeripheralPIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed PinsUnit Electrical SpecificationsAbsolute Maximum Ratings1 Recommended Operating Conditions1GDH, CV Parameter Test Conditions MIN TYP MAX UnitDvdd II, IOZParameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling MIN MAX Unit ResetReset Electrical Data/Timing Reset Timing RequirementsDMAX Device-Specific Information Dual Data Movement Accelerator dMAXREQ RAM DMAXRAM REQSubmit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input AssignmentsDMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts Emif Device-Specific Information External Memory Interface EmifEmwe ResetDSP Emif EmrasEMWEDQM1 EmcasEmclk EMWEDQM0Emif Registers Emif Peripheral Registers DescriptionsParameter MIN MAX Unit Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Emif Sdram Interface Timing RequirementsEmif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode13. Emwait Timing Requirements Uhpi Major Modes on C672x 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Device-Specific InformationUhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT DSPUHPIHD16/HHWIL UhpihasbExternal Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword ModeExternal Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword ModeUhpi Internal Registers 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Peripheral Registers DescriptionsBytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value WriteHpiaumb Description BIT no Name Reset Read Value Write318 Reserved Hpiamsb DescriptionUniversal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSPMcASP Internal Registers Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions Register Byte Description Name AddressDITCSRA1 XclkchkXevtctl DITCSRA00x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 Description AMUTEIN1AMUTEIN2 AMUTEIN2Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input TimingsACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output TimingsSPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1Master SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option229. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C115.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address 34. I2C Input Timing Requirements 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing Inter-Integrated Circuit I2C TimingParameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt RTI Internal Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions 36. RTI RegistersRtiwdstatus RtiintflagRtidwdctrl Rtidwdprld38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin39. Clkin Timing Requirements Clock Electrical Data/TimingPLL Device-Specific Information Phase-Locked Loop PLLEMI Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions Board41. PLL Controller Registers PLL Registers DescriptionsRTI CODEC, DIRADC, DAC, DSD SpioADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff HeightPackaging Information PowerPAD PCB FootprintPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice