Contents
Features
TMS320C6727, TMS320C6726, TMS320C6722 DSPs
Description
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Device Compatibility
Functional Block Diagram
Contents
Package Thermal Resistance Characteristics
Hardware Features
Device Characteristics
Characteristics of the C672x Processors
C6726
Enhanced C67x+ CPU
CPU Data Paths
CPU Interrupt Assignments
CPU Interrupt Assignments
New Floating-Point Instructions for C67x+ CPU
Instruction FLOATING-POINT Improves Operation
Internal Program/Data ROM and RAM
Byte Bank
Program Cache Control Registers
Cache Mode
Program Cache
Register Name Byte Address Description
High-Performance Crossbar Switch
Block Diagram of Crossbar Switch
Bus Bridges
Label Bridge Description Master Clock Target Clock
BIT no Name Reset Value Read Write Description
Csprst
Memory Map Summary
C672x Memory Map
Ffff
Boot Mode Uhpihcs
Boot Modes
Required Boot Pin Settings at Device Reset
SPI0SIMO SPI0CLK
BIT no Name Description
PINCAP7
PINCAP15
Pin Assignments
Pin Maps
Pin Low-Profile Quad Flatpack RFP Suffix-Top View
12. Terminal Functions
Signal Name RFP GDH
Terminal Functions
ZDH
IO/I IPD
Description ZDH
AFSR0
AHCLKR0/AHCLKR1
ACLKR0
AHCLKX0/AHCLKX2
Power Pins 256-Terminal GDH/ZDH Package
Power Pins 144-Pin RFP Package
Development
Development Support
Device Support
Device Family
TMS 320 C6727 GDH a 250
Prefix Device Speed Range
Package Type ‡ §
Documentation Support
C672x devices are documented in the tools v6.0 documentation
Options for Configuring SPI0, I2C0, and I2C1
Device Configuration Registers
Device-Level Configuration Registers
Peripheral Pin Multiplexing Options
Configuration Option Peripheral
Options for Configuring SPI1, McASP0, and McASP1 Data Pins
Options for Configuring Emif and Uhpi C6727 Only
Peripheral Pin Multiplexing Control
Priority of Control of Data Output on Multiplexed Pins
PIN First Priority Second Priority Third Priority
Recommended Operating Conditions1
Electrical Specifications
Absolute Maximum Ratings1
Unit
II, IOZ
Parameter Test Conditions MIN TYP MAX Unit
Dvdd
GDH, CV
Parameter Information
Parameter Information Device-Specific Information
Tester Pin Electronics
Timing Parameter Symbology
Power Supplies
Power-Supply Sequencing
Power-Supply Decoupling
Reset Timing Requirements
Reset
Reset Electrical Data/Timing
MIN MAX Unit
Dual Data Movement Accelerator dMAX
DMAX Device-Specific Information
REQ
DMAX
RAM
REQ RAM
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DMAX Peripheral Event Input Assignments
Event Number Event Acronym Event Description
DMAX Configuration Registers
DMAX Peripheral Registers Descriptions
Byte Address Register Name Description
External Interrupts
External Memory Interface Emif
Emif Device-Specific Information
Emras
Reset
DSP Emif
Emwe
EMWEDQM0
Emcas
Emclk
EMWEDQM1
Emif Peripheral Registers Descriptions
Emif Registers
Emif Sdram Interface Timing Requirements
Emif Sdram Interface Switching Characteristics
Emif Electrical Data/Timing
Parameter MIN MAX Unit
Emif Asynchronous Interface Switching Characteristics1
Emif Asynchronous Interface Timing Requirements1
Basic Sdram Write Operation Emclk
Emras Emcas Emwe
Basic Sdram Read Operation
Asynchronous Read WE Strobe Mode
10. Asynchronous Read Select Strobe Mode
11. Asynchronous Write WE Strobe Mode
12. Asynchronous Write Select Strobe Mode
13. Emwait Timing Requirements
Uhpi Device-Specific Information
10. HPI Access Types Selected by UHPIHCNTL10
Universal Host-Port Interface Uhpi C6727 Only
Uhpi Major Modes on C672x
Uhpihasb
DSP
UHPIHD16/HHWIL
Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT
16. Uhpi Multiplexed Host Address/Data Fullword Mode
External Host MCU AxyC D150 D16 D3117 BE30D
17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode
External Host MCU A172 AxyA D150 D16 D3117 BE30C
Uhpi Peripheral Registers Descriptions
11. Uhpi Configuration Registers
Device-Level Configuration Registers Controlling Uhpi
Uhpi Internal Registers
BIT no Name Reset Read Description Value Write
Bytead Full Nmux Pagem ENA
Hpiamsb Description
BIT no Name Reset Read Value Write
318 Reserved
Hpiaumb Description
Uhpi Electrical Data/Timing
Universal Host-Port Interface Uhpi Read and Write Timing
15. Uhpi Read and Write Timing Requirements1
16. Uhpi Read and Write Switching Characteristics1
UHPIHDSx
Read Write UHPIHA150
Valid Read data Write data
22. Multiplexed Read Timings Using Uhpihas
Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a
23. Multiplexed Read Timings With Uhpihas Held High
24. Multiplexed Write Timings With Uhpihas Held High
Multichannel Audio Serial Ports McASP0, McASP1, and McASP2
GIO
17. McASP Configurations on C672x DSP
DIT Clock Pins Data Pins Comments
Register Byte Description Name Address
Device-Level Configuration Registers Controlling McASP
McASP Peripheral Registers Descriptions
McASP Internal Registers
DITCSRA0
Xclkchk
Xevtctl
DITCSRA1
0x4500 020C XBUF3 Transmit buffer register for serializer
AMUTEIN0
313 Reserved
AMUTEIN0 Description
AMUTEIN1
AMUTEIN1 Description
AMUTEIN2
AMUTEIN2
McASP Electrical Data/Timing
Multichannel Audio Serial Port McASP Timing
22. McASP Timing Requirements1
23. McASP Switching Characteristics1
29. McASP Input Timings
ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B
30. McASP Output Timings
ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B
Serial Peripheral Interface Ports SPI0, SPI1
SPI Device-Specific Information
SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO
Master SPI
Slave SPI
24. SPIx Configuration Registers
SPI Peripheral Registers Descriptions
SPI0 SPI1 Register Name Description Byte Address
SPI Electrical Data/Timing
Serial Peripheral Interface SPI Timing
25. General Timing Requirements for SPIx Master Modes1
26. General Timing Requirements for SPIx Slave Modes1
27. Additional1 SPI Master Timings, 4-Pin Enable Option2
MIN MAX Unit 2P
29. Additional1 SPI Master Timings, 5-Pin Option2
30. Additional1 SPI Slave Timings, 4-Pin Enable Option2
31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2
32. Additional1 SPI Slave Timings, 5-Pin Option2
33. SPI Timings-Master Mode
34. SPI Timings-Slave Mode
35. SPI Timings-Master Mode 4-Pin and 5-Pin
36. SPI Timings-Slave Mode 4-Pin and 5-Pin
Inter-Integrated Circuit Serial Ports I2C0, I2C1
15.1 I2C Device-Specific Information
33. I2Cx Configuration Registers
15.2 I2C Peripheral Registers Descriptions
Register Name Description Byte Address
Inter-Integrated Circuit I2C Timing
35. I2C Switching Characteristics1
15.3 I2C Electrical Data/Timing
34. I2C Input Timing Requirements
35. I2C Switching Characteristics
Parameter
I2CxSDA I2CxSCL Stop Start Repeated
Real-Time Interrupt RTI Timer With Digital Watchdog
16.1 RTI/Digital Watchdog Device-Specific Information
Watchdog Key Register Bit Key RTI Interrupt
36. RTI Registers
Device-Level Configuration Registers Controlling RTI
16.2 RTI/Digital Watchdog Registers Descriptions
RTI Internal Registers
Rtidwdprld
Rtiintflag
Rtidwdctrl
Rtiwdstatus
External Clock Input From Oscillator or Clkin Pin
38. Recommended On-Chip Oscillator Components
Clock Electrical Data/Timing
39. Clkin Timing Requirements
Phase-Locked Loop PLL
PLL Device-Specific Information
Board
Parameter Default Value Allowed Setting or Range
40. Allowed PLL Operating Conditions
EMI
PLL Registers Descriptions
41. PLL Controller Registers
Spio
CODEC, DIR
ADC, DAC, DSD
RTI
ADDS/CHANGES/DELETES
Package Thermal Resistance Characteristics
Thermal Characteristics for GDH/ZDH Package
Thermal Characteristics for RFP Package
Standoff Height
Standoff Height
PowerPAD PCB Footprint
Packaging Information
Page
Orderable Device Status Package Pins Package Eco Plan
MSL Peak Temp
Qty
Page
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Important Notice