Texas Instruments TMS320C6727 Device Configuration Registers, Peripheral Pin Multiplexing Options

Page 30

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

3 Device Configurations

3.1 Device Configuration Registers

The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1. These registers need to be programmed as part of the device initialization procedure. See Section 3.2.

Table 3-1. Device-Level Configuration Registers

REGISTER NAME

BYTE ADDRESS

DESCRIPTION

DEFINED

CFGPIN0

0x4000

0000

Captures values of eight pins on rising edge of RESET pin.

Table 2-10

CFGPIN1

0x4000

0004

Captures values of eight pins on rising edge of RESET pin.

Table 2-11

CFGHPI

0x4000

0008

Controls enable of UHPI and selection of its operating mode.

Table 4-12

CFGHPIAMSB

0x4000

000C

Controls upper byte of UHPI address into C672x address space in

Table 4-13

 

 

 

Non-Multiplexed Mode or if explicitly enabled for security purposes.

 

CFGHPIAUMB

0x4000

0010

Controls upper middle byte of UHPI address into C672x address space

Table 4-14

 

 

 

in Non-Multiplexed Mode or if explicitly enabled for security purposes.

 

CFGRTI

0x4000

0014

Selects the sources for the RTI Input Captures from among the six

Table 4-37

 

 

 

McASP DMA events.

 

CFGMCASP0

0x4000

0018

Selects the peripheral pin to be used as AMUTEIN0.

Table 4-19

CFGMCASP1

0x4000

001C

Selects the peripheral pin to be used as AMUTEIN1.

Table 4-20

CFGMCASP2(1)

0x4000

0020

Selects the peripheral pin to be used as AMUTEIN2.

Table 4-21

CFGBRIDGE

0x4000

0024

Controls reset of the bridge BR2 in Figure 2-4. This bridge must be reset

Table 2-7

 

 

 

explicitly after any change to the PLL controller affecting SYSCLK1 and

 

 

 

 

SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port

 

 

 

 

(CSP).

 

(1)CFGMCASP2 is reserved on the C6722.

3.2 Peripheral Pin Multiplexing Options

This section describes the options for configuring peripherals which share pins on the C672x DSP. Table 3-2lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins.

Table 3-2. Options for Configuring SPI0, I2C0, and I2C1

 

 

 

CONFIGURATION

 

 

OPTION 1

OPTION 2

OPTION 3

PERIPHERAL

SPI0

3-, 4,- or 5-pin mode

3-pin mode

disabled

 

I2C0

disabled

disabled

enabled

 

I2C1

disabled

enabled

enabled

PINS

SPI0_SOMI/I2C0_SDA

SPI0_SOMI

SPI0_SOMI

I2C0_SDA

 

SPI0_SIMO

SPI0_SIMO

SPI0_SIMO

GPIO through SPI0_SIMO pin control

 

SPI0_CLK/I2C0_SCL

SPI0_CLK

SPI0_CLK

I2C0_SCL

 

SPI0_SCS/I2C1_SCL

SPI0_SCS

I2C1_SCL

I2C1_SCL

 

SPI0_ENA/I2C1_SDA

SPI0_ENA

I2C1_SDA

I2C1_SDA

30

Device Configurations

Submit Documentation Feedback

Page 29 Page 31
Image 30
Page 29 Page 31
Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsHardware Features Device CharacteristicsCharacteristics of the C672x Processors C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankProgram Cache Control Registers Cache ModeProgram Cache Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstMemory Map Summary C672x Memory MapFfff Boot Mode Uhpihcs Boot ModesRequired Boot Pin Settings at Device Reset SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View 12. Terminal Functions Signal Name RFP GDHTerminal Functions ZDHIO/I IPD Description ZDH AFSR0 AHCLKR0/AHCLKR1ACLKR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevelopment Development SupportDevice Support Device Family TMS 320 C6727 GDH a 250Prefix Device Speed Range Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Options for Configuring SPI0, I2C0, and I2C1 Device Configuration RegistersDevice-Level Configuration Registers Peripheral Pin Multiplexing OptionsConfiguration Option Peripheral Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityRecommended Operating Conditions1 Electrical SpecificationsAbsolute Maximum Ratings1 UnitII, IOZ Parameter Test Conditions MIN TYP MAX UnitDvdd GDH, CVParameter Information Parameter Information Device-Specific InformationTester Pin Electronics Timing Parameter Symbology Power Supplies Power-Supply SequencingPower-Supply Decoupling Reset Timing Requirements ResetReset Electrical Data/Timing MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationREQ DMAXRAM REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionDMAX Configuration Registers DMAX Peripheral Registers DescriptionsByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific InformationEmras ResetDSP Emif EmweEMWEDQM0 EmcasEmclk EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Timing Requirements Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Basic Sdram Write Operation Emclk Emras Emcas EmweBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements Uhpi Device-Specific Information 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Major Modes on C672xUhpihasb DSPUHPIHD16/HHWIL Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30CUhpi Peripheral Registers Descriptions 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENAHpiamsb Description BIT no Name Reset Read Value Write318 Reserved Hpiaumb DescriptionUhpi Electrical Data/Timing Universal Host-Port Interface Uhpi Read and Write Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 UHPIHDSx Read Write UHPIHA150Valid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsRegister Byte Description Name Address Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions McASP Internal RegistersDITCSRA0 XclkchkXevtctl DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 313 ReservedAMUTEIN0 Description AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN2McASP Electrical Data/Timing Multichannel Audio Serial Port McASP Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationSPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO Master SPISlave SPI 24. SPIx Configuration Registers SPI Peripheral Registers DescriptionsSPI0 SPI1 Register Name Description Byte Address SPI Electrical Data/Timing Serial Peripheral Interface SPI Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information33. I2Cx Configuration Registers 15.2 I2C Peripheral Registers DescriptionsRegister Name Description Byte Address Inter-Integrated Circuit I2C Timing 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing 34. I2C Input Timing Requirements35. I2C Switching Characteristics ParameterI2CxSDA I2CxSCL Stop Start Repeated Real-Time Interrupt RTI Timer With Digital Watchdog 16.1 RTI/Digital Watchdog Device-Specific InformationWatchdog Key Register Bit Key RTI Interrupt 36. RTI Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions RTI Internal RegistersRtidwdprld RtiintflagRtidwdctrl RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationBoard Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions EMIPLL Registers Descriptions 41. PLL Controller RegistersSpio CODEC, DIRADC, DAC, DSD RTIADDS/CHANGES/DELETES Package Thermal Resistance Characteristics Thermal Characteristics for GDH/ZDH PackageThermal Characteristics for RFP Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Page Important Notice
Top Page Image Contents