Texas Instruments TMS320C6727 Rtiintflag, Rtidwdctrl, Rtidwdprld, Rtiwdstatus, Rtiwdkey, CAPSEL1

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		TMS320C6727, TMS320C6726, TMS320C6722
www.ti.com		Floating-Point Digital Signal Processors
www.ti.com		SPRS268E –MAY 2005 –REVISED JANUARY 2007
		SPRS268E –MAY 2005 –REVISED JANUARY 2007
	Table 4-36. RTI Registers (continued)
BYTE ADDRESS	REGISTER NAME	DESCRIPTION
0x4200 0088	RTIINTFLAG	Interrupt Flags. Interrupt pending bits.
0x4200 0090	RTIDWDCTRL	Digital Watchdog Control. Enables the Digital Watchdog.
0x4200 0094	RTIDWDPRLD	Digital Watchdog Preload. Sets the experation time of the Digital Watchdog.
0x4200 0098	RTIWDSTATUS	Watchdog Status. Reflects the status of Analog and Digital Watchdog.
0x4200 009C	RTIWDKEY	Watchdog Key. Correct written key values discharge the external capacitor.
0x4200 00A0	RTIDWDCNTR	Digital Watchdog Down-Counter

Figure 4-41shows the bit layout of the CFGRTI register and Table 4-37contains a description of the bits.

31					8
			Reserved
7	6	4	3	2	0
Reserved	CAPSEL1		Reserved		CAPSEL0
	R/W, 0				R/W, 0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 4-41. CFGRTI Register Bit Layout (0x4000 0014)

Table 4-37. CFGRTI Register Bit Field Description (0x4000 0014)

	BIT NO.	NAME	RESET	READ
	BIT NO.	NAME	VALUE	WRITE
			VALUE	WRITE
	31:7,3	Reserved	N/A	N/A
	6:4	CAPSEL1	0	R/W
	2:0	CAPSEL0	0	R/W

DESCRIPTION

Reads are indeterminate. Only 0s should be written to these bits.

CAPSEL0 selects the input to the RTI Input Capture 0 function. CAPSEL1 selects the input to the RTI Input Capture 1 function.

The encoding is the same for both fields:

000 = Select McASP0 Transmit DMA Event

001 = Select McASP0 Receive DMA Event

010 = Select McASP1 Transmit DMA Event

011 = Select McASP1 Receive DMA Event

100 = Select McASP2 Transmit DMA Event

101 = Select McASP2 Receive DMA Event

Other values are reserved and their effect is not determined.

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Peripheral and Electrical Specifications

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Contents TMS320C6727, TMS320C6726, TMS320C6722 DSPs FeaturesDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics ContentsC6726 Device CharacteristicsCharacteristics of the C672x Processors Hardware FeaturesCPU Data Paths Enhanced C67x+ CPUInstruction FLOATING-POINT Improves Operation CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsByte Bank Internal Program/Data ROM and RAMRegister Name Byte Address Description Cache ModeProgram Cache Program Cache Control RegistersBlock Diagram of Crossbar Switch High-Performance Crossbar SwitchLabel Bridge Description Master Clock Target Clock Bus BridgesCsprst BIT no Name Reset Value Read Write DescriptionMemory Map Summary C672x Memory MapFfff SPI0SIMO SPI0CLK Boot ModesRequired Boot Pin Settings at Device Reset Boot Mode UhpihcsPINCAP7 BIT no Name DescriptionPINCAP15 Pin Maps Pin AssignmentsPin Low-Profile Quad Flatpack RFP Suffix-Top View ZDH Signal Name RFP GDHTerminal Functions 12. Terminal FunctionsIO/I IPD Description ZDH AHCLKX0/AHCLKX2 AHCLKR0/AHCLKR1ACLKR0 AFSR0Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH PackageDevelopment Development SupportDevice Support Package Type ‡ § TMS 320 C6727 GDH a 250Prefix Device Speed Range Device FamilyDocumentation Support C672x devices are documented in the tools v6.0 documentation Peripheral Pin Multiplexing Options Device Configuration RegistersDevice-Level Configuration Registers Options for Configuring SPI0, I2C0, and I2C1Peripheral Pin Multiplexing Control Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Configuration Option PeripheralPIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed PinsUnit Electrical SpecificationsAbsolute Maximum Ratings1 Recommended Operating Conditions1GDH, CV Parameter Test Conditions MIN TYP MAX UnitDvdd II, IOZParameter Information Parameter Information Device-Specific InformationTester Pin Electronics Timing Parameter Symbology Power Supplies Power-Supply SequencingPower-Supply Decoupling MIN MAX Unit ResetReset Electrical Data/Timing Reset Timing RequirementsDMAX Device-Specific Information Dual Data Movement Accelerator dMAXREQ RAM DMAXRAM REQSubmit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input AssignmentsDMAX Configuration Registers DMAX Peripheral Registers DescriptionsByte Address Register Name Description External Interrupts Emif Device-Specific Information External Memory Interface EmifEmwe ResetDSP Emif EmrasEMWEDQM1 EmcasEmclk EMWEDQM0Emif Registers Emif Peripheral Registers DescriptionsParameter MIN MAX Unit Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Emif Sdram Interface Timing RequirementsEmif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1Basic Sdram Write Operation Emclk Emras Emcas EmweBasic Sdram Read Operation 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode13. Emwait Timing Requirements Uhpi Major Modes on C672x 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Device-Specific InformationUhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT DSPUHPIHD16/HHWIL UhpihasbExternal Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword ModeExternal Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword ModeUhpi Internal Registers 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Peripheral Registers DescriptionsBytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value WriteHpiaumb Description BIT no Name Reset Read Value Write318 Reserved Hpiamsb DescriptionUhpi Electrical Data/Timing Universal Host-Port Interface Uhpi Read and Write Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 UHPIHDSx Read Write UHPIHA150Valid Read data Write data Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSPMcASP Internal Registers Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions Register Byte Description Name AddressDITCSRA1 XclkchkXevtctl DITCSRA00x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 313 ReservedAMUTEIN0 Description AMUTEIN1 Description AMUTEIN1AMUTEIN2 AMUTEIN2McASP Electrical Data/Timing Multichannel Audio Serial Port McASP Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input TimingsACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output TimingsSPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO Master SPISlave SPI 24. SPIx Configuration Registers SPI Peripheral Registers DescriptionsSPI0 SPI1 Register Name Description Byte Address SPI Electrical Data/Timing Serial Peripheral Interface SPI Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option229. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C133. I2Cx Configuration Registers 15.2 I2C Peripheral Registers DescriptionsRegister Name Description Byte Address 34. I2C Input Timing Requirements 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing Inter-Integrated Circuit I2C Timing35. I2C Switching Characteristics ParameterI2CxSDA I2CxSCL Stop Start Repeated Real-Time Interrupt RTI Timer With Digital Watchdog 16.1 RTI/Digital Watchdog Device-Specific InformationWatchdog Key Register Bit Key RTI Interrupt RTI Internal Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions 36. RTI RegistersRtiwdstatus RtiintflagRtidwdctrl Rtidwdprld38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin39. Clkin Timing Requirements Clock Electrical Data/TimingPLL Device-Specific Information Phase-Locked Loop PLLEMI Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions Board41. PLL Controller Registers PLL Registers DescriptionsRTI CODEC, DIRADC, DAC, DSD SpioADDS/CHANGES/DELETES Package Thermal Resistance Characteristics Thermal Characteristics for GDH/ZDH PackageThermal Characteristics for RFP Package Standoff Height Standoff HeightPackaging Information PowerPAD PCB FootprintPage Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Page Important Notice