Texas Instruments Carrier 23xrv Manual for TMS320C6722, TMS320C6726, and TMS320C6727 Systems
Page 83

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.14.3 SPI Electrical Data/Timing

4.14.3.1 Serial Peripheral Interface (SPI) Timing

Table 4-25through Table 4-32assume testing over recommended operating conditions (see Figure 4-33through Figure 4-36).

Table 4-25. General Timing Requirements for SPIx Master Modes(1)

NO.

1tc(SPC)M

2 tw(SPCH)M

3 tw(SPCL)M

Cycle Time, SPIx_CLK, All Master Modes

Pulse Width High, SPIx_CLK, All Master Modes

Pulse Width Low, SPIx_CLK, All Master Modes

MIN

greater of 8P or 100 ns

greater of 4P or 45 ns

greater of 4P or 45 ns

MAX UNIT

256P ns

ns

ns

4td(SIMO_SPC)M

5td(SPC_SIMO)M

6toh(SPC_SIMO)M

7tsu(SOMI_SPC)M

8tih(SPC_SOMI)M

Delay, initial data bit valid on SPIx_SIMO to initial edge on SPIx_CLK(2)

Delay, subsequent bits valid on SPIx_SIMO after transmit edge of SPIx_CLK

Output hold time, SPIx_SIMO valid after receive edge of SPIxCLK, except for final bit(3)

Input Setup Time,

SPIx_SOMI valid before receive edge of SPIx_CLK

Input Hold Time, SPIx_SOMI valid after receive edge of SPIx_CLK

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK rising

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK falling

Polarity = 1, Phase = 1, from SPIx_CLK rising

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK rising

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK falling

Polarity = 0, Phase = 0, to SPIx_CLK falling

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK rising

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK rising

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK falling

4P

0.5tc(SPC)M + 4P

4P

0.5tc(SPC)M + 4P

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5tc(SPC)M – 10

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 15

0.5P + 5

0.5P + 5

0.5P + 5

0.5P + 5

ns

15

15

ns

15

15

ns

ns

ns

(1)P = SYSCLK2 period

(2)First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.

(3)The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.

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Peripheral and Electrical Specifications

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Contents TMS320C6727, TMS320C6726, TMS320C6722 DSPs FeaturesDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics ContentsC6726 Device CharacteristicsCharacteristics of the C672x Processors Hardware FeaturesCPU Data Paths Enhanced C67x+ CPUInstruction FLOATING-POINT Improves Operation CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsByte Bank Internal Program/Data ROM and RAMRegister Name Byte Address Description Cache ModeProgram Cache Program Cache Control RegistersBlock Diagram of Crossbar Switch High-Performance Crossbar SwitchLabel Bridge Description Master Clock Target Clock Bus BridgesCsprst BIT no Name Reset Value Read Write DescriptionFfff Memory Map SummaryC672x Memory Map SPI0SIMO SPI0CLK Boot ModesRequired Boot Pin Settings at Device Reset Boot Mode UhpihcsPINCAP7 BIT no Name DescriptionPINCAP15 Pin Maps Pin AssignmentsPin Low-Profile Quad Flatpack RFP Suffix-Top View ZDH Signal Name RFP GDHTerminal Functions 12. Terminal FunctionsIO/I IPD Description ZDH AHCLKX0/AHCLKX2 AHCLKR0/AHCLKR1ACLKR0 AFSR0Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH PackageDevice Support DevelopmentDevelopment Support Package Type ‡ § TMS 320 C6727 GDH a 250Prefix Device Speed Range Device FamilyDocumentation Support C672x devices are documented in the tools v6.0 documentation Peripheral Pin Multiplexing Options Device Configuration RegistersDevice-Level Configuration Registers Options for Configuring SPI0, I2C0, and I2C1Peripheral Pin Multiplexing Control Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Configuration Option PeripheralPIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed PinsUnit Electrical SpecificationsAbsolute Maximum Ratings1 Recommended Operating Conditions1GDH, CV Parameter Test Conditions MIN TYP MAX UnitDvdd II, IOZTester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing MIN MAX Unit ResetReset Electrical Data/Timing Reset Timing RequirementsDMAX Device-Specific Information Dual Data Movement Accelerator dMAXREQ RAM DMAXRAM REQSubmit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input AssignmentsByte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts Emif Device-Specific Information External Memory Interface EmifEmwe ResetDSP Emif EmrasEMWEDQM1 EmcasEmclk EMWEDQM0Emif Registers Emif Peripheral Registers DescriptionsParameter MIN MAX Unit Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Emif Sdram Interface Timing RequirementsEmif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode13. Emwait Timing Requirements Uhpi Major Modes on C672x 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Device-Specific InformationUhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT DSPUHPIHD16/HHWIL UhpihasbExternal Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword ModeExternal Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword ModeUhpi Internal Registers 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Peripheral Registers DescriptionsBytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value WriteHpiaumb Description BIT no Name Reset Read Value Write318 Reserved Hpiamsb Description15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSPMcASP Internal Registers Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions Register Byte Description Name AddressDITCSRA1 XclkchkXevtctl DITCSRA00x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 Description AMUTEIN1AMUTEIN2 AMUTEIN222. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input TimingsACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output TimingsSPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1Slave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option229. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C1Register Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions 34. I2C Input Timing Requirements 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing Inter-Integrated Circuit I2C TimingI2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information RTI Internal Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions 36. RTI RegistersRtiwdstatus RtiintflagRtidwdctrl Rtidwdprld38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin39. Clkin Timing Requirements Clock Electrical Data/TimingPLL Device-Specific Information Phase-Locked Loop PLLEMI Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions Board41. PLL Controller Registers PLL Registers DescriptionsRTI CODEC, DIRADC, DAC, DSD SpioADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff HeightPackaging Information PowerPAD PCB FootprintPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice
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