Texas Instruments TMS320C6722, TMS320C6727 Additional1 SPI Master Timings, 4-Pin Enable Option2

Page 85

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-27. Additional(1) SPI Master Timings, 4-Pin Enable Option(2) (3)

NO.

MIN

MAX UNIT

Delay from slave assertion of

17 td(ENA_SPC)M SPIx_ENA active to first SPIx_CLK from master.(4)

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

3P + 15

0.5tc(SPC)M + 3P + 15

ns

3P + 15

0.5tc(SPC)M + 3P + 15

Max delay for slave to deassert

SPIx_ENA after final SPIx_CLK

18 td(SPC_ENA)M edge to ensure master does not begin the next transfer.(5)

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

0.5tc(SPC)M

0

ns

0.5tc(SPC)M

0

(1)These parameters are in addition to the general timings for SPI master modes (Table 4-25).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)In the case where the master SPI is ready with new data before SPIx_ENA assertion.

(5)In the case where the master SPI is ready with new data before SPIx_ENA deassertion.

Table 4-28. Additional(1) SPI Master Timings, 4-Pin Chip Select Option(2) (3)

NO.

19td(SCS_SPC)M

20td(SPC_SCS)M

Delay from SPIx_SCS active to first SPIx_CLK(4)(5)

Delay from final SPIx_CLK edge to master deasserting SPIx_SCS(6)(7)

Polarity = 0, Phase = 0, to SPIx_CLK rising

Polarity = 0, Phase = 1, to SPIx_CLK rising

Polarity = 1, Phase = 0, to SPIx_CLK falling

Polarity = 1, Phase = 1, to SPIx_CLK falling

Polarity = 0, Phase = 0, from SPIx_CLK falling

Polarity = 0, Phase = 1, from SPIx_CLK falling

Polarity = 1, Phase = 0, from SPIx_CLK rising

Polarity = 1, Phase = 1, from SPIx_CLK rising

MIN MAX UNIT 2P – 10

0.5tc(SPC)M + 2P – 10

ns

2P – 10

0.5tc(SPC)M + 2P – 10

0.5tc(SPC)M

0

ns

0.5tc(SPC)M

0

(1)These parameters are in addition to the general timings for SPI master modes (Table 4-25).

(2)P = SYSCLK2 period

(3)Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.

(4)In the case where the master SPI is ready with new data before SPIx_SCS assertion.

(5)This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].

(6)Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain asserted.

(7)This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].

Submit Documentation Feedback

Peripheral and Electrical Specifications

85

Page 84 Page 86
Image 85
Page 84 Page 86
Contents TMS320C6727, TMS320C6726, TMS320C6722 DSPs FeaturesDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics ContentsCharacteristics of the C672x Processors Device CharacteristicsHardware Features C6726CPU Data Paths Enhanced C67x+ CPUNew Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsCPU Interrupt Assignments Instruction FLOATING-POINT Improves OperationByte Bank Internal Program/Data ROM and RAMProgram Cache Cache ModeProgram Cache Control Registers Register Name Byte Address DescriptionBlock Diagram of Crossbar Switch High-Performance Crossbar SwitchLabel Bridge Description Master Clock Target Clock Bus BridgesCsprst BIT no Name Reset Value Read Write DescriptionC672x Memory Map Memory Map SummaryFfff Required Boot Pin Settings at Device Reset Boot ModesBoot Mode Uhpihcs SPI0SIMO SPI0CLKPINCAP7 BIT no Name DescriptionPINCAP15 Pin Maps Pin AssignmentsPin Low-Profile Quad Flatpack RFP Suffix-Top View Terminal Functions Signal Name RFP GDH12. Terminal Functions ZDHIO/I IPD Description ZDH ACLKR0 AHCLKR0/AHCLKR1AFSR0 AHCLKX0/AHCLKX2Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH PackageDevelopment Support DevelopmentDevice Support Prefix Device Speed Range TMS 320 C6727 GDH a 250Device Family Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Device-Level Configuration Registers Device Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing OptionsOptions for Configuring Emif and Uhpi C6727 Only Options for Configuring SPI1, McASP0, and McASP1 Data PinsConfiguration Option Peripheral Peripheral Pin Multiplexing ControlPIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed PinsAbsolute Maximum Ratings1 Electrical SpecificationsRecommended Operating Conditions1 UnitDvdd Parameter Test Conditions MIN TYP MAX UnitII, IOZ GDH, CVParameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Electrical Data/Timing ResetReset Timing Requirements MIN MAX UnitDMAX Device-Specific Information Dual Data Movement Accelerator dMAXRAM DMAXREQ REQ RAMSubmit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input AssignmentsDMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts Emif Device-Specific Information External Memory Interface EmifDSP Emif ResetEmras EmweEmclk EmcasEMWEDQM0 EMWEDQM1Emif Registers Emif Peripheral Registers DescriptionsEmif Electrical Data/Timing Emif Sdram Interface Switching CharacteristicsEmif Sdram Interface Timing Requirements Parameter MIN MAX UnitEmif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode13. Emwait Timing Requirements Universal Host-Port Interface Uhpi C6727 Only 10. HPI Access Types Selected by UHPIHCNTL10Uhpi Device-Specific Information Uhpi Major Modes on C672xUHPIHD16/HHWIL DSPUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINTExternal Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword ModeExternal Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword ModeDevice-Level Configuration Registers Controlling Uhpi 11. Uhpi Configuration RegistersUhpi Peripheral Registers Descriptions Uhpi Internal RegistersBytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value Write318 Reserved BIT no Name Reset Read Value WriteHpiamsb Description Hpiaumb DescriptionUniversal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSPMcASP Peripheral Registers Descriptions Device-Level Configuration Registers Controlling McASPRegister Byte Description Name Address McASP Internal RegistersXevtctl XclkchkDITCSRA0 DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 Description AMUTEIN1AMUTEIN2 AMUTEIN2Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input TimingsACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output TimingsSPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1Master SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option229. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C115.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address 15.3 I2C Electrical Data/Timing 35. I2C Switching Characteristics1Inter-Integrated Circuit I2C Timing 34. I2C Input Timing RequirementsParameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt 16.2 RTI/Digital Watchdog Registers Descriptions Device-Level Configuration Registers Controlling RTI36. RTI Registers RTI Internal RegistersRtidwdctrl RtiintflagRtidwdprld Rtiwdstatus38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin39. Clkin Timing Requirements Clock Electrical Data/TimingPLL Device-Specific Information Phase-Locked Loop PLL40. Allowed PLL Operating Conditions Parameter Default Value Allowed Setting or RangeBoard EMI41. PLL Controller Registers PLL Registers DescriptionsADC, DAC, DSD CODEC, DIRSpio RTIADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff HeightPackaging Information PowerPAD PCB FootprintPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice
Top Page Image Contents