Texas Instruments TMS320C6722 McASP Peripheral Registers Descriptions, McASP Internal Registers

Page 70

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.13.1 McASP Peripheral Registers Description(s)

Table 4-18is a list of the McASP registers. For more information about these registers, see the TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU878).

Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus

 

McASP0

McASP1

McASP2

REGISTER

 

 

BYTE

BYTE

BYTE

DESCRIPTION

 

NAME

 

ADDRESS

ADDRESS

ADDRESS

 

 

 

 

 

 

 

Device-Level Configuration Registers Controlling McASP

 

0x4000 0018

0x4000 001C

0x4000 0020

CFGMCASPx

Selects the peripheral pin to be used as AMUTEINx

 

 

 

 

McASP Internal Registers

 

0x4400 0000

0x4500 0000

0x4600 0000

PID

Peripheral identification register

 

0x4400 0004

0x4500 0004

0x4600 0004

PWRDEMU

Power down and emulation management register

 

0x4400 0010

0x4500 0010

0x4600 0010

PFUNC

Pin function register

 

0x4400 0014

0x4500 0014

0x4600 0014

PDIR

Pin direction register

 

0x4400 0018

0x4500 0018

0x4600 0018

PDOUT

Pin data output register

 

0x4400 001C

0x4500 001C

0x4600 001C

PDIN (reads)

Read returns: Pin data input register

 

 

 

 

PDSET (writes)

Writes affect: Pin data set register

 

 

 

 

 

(alternate write address: PDOUT)

 

0x4400 0020

0x4500 0020

0x4600 0020

PDCLR

Pin data clear register (alternate write address: PDOUT)

 

0x4400 0044

0x4500 0044

0x4600 0044

GBLCTL

Global control register

 

0x4400 0048

0x4500 0048

0x4600 0048

AMUTE

Audio mute control register

 

0x4400 004C

0x4500 004C

0x4600 004C

DLBCTL

Digital loopback control register

 

0x4400 0050

0x4500 0050

0x4600 0050

DITCTL

DIT mode control register

 

0x4400 0060

0x4500 0060

0x4600 0060

RGBLCTL

Receiver global control register: Alias of GBLCTL, only

 

 

 

 

 

receive bits are affected - allows receiver to be reset

 

 

 

 

 

independently from transmitter

 

0x4400 0064

0x4500 0064

0x4600 0064

RMASK

Receive format unit bit mask register

 

0x4400 0068

0x4500 0068

0x4600 0068

RFMT

Receive bit stream format register

 

0x4400 006C

0x4500 006C

0x4600 006C

AFSRCTL

Receive frame sync control register

 

0x4400 0070

0x4500 0070

0x4600 0070

ACLKRCTL

Receive clock control register

 

0x4400 0074

0x4500 0074

0x4600 0074

AHCLKRCTL

Receive high-frequency clock control register

 

0x4400 0078

0x4500 0078

0x4600 0078

RTDM

Receive TDM time slot 0-31 register

 

0x4400 007C

0x4500 007C

0x4600 007C

RINTCTL

Receiver interrupt control register

 

0x4400 0080

0x4500 0080

0x4600 0080

RSTAT

Receiver status register

 

0x4400 0084

0x4500 0084

0x4600 0084

RSLOT

Current receive TDM time slot register

 

0x4400 0088

0x4500 0088

0x4600 0088

RCLKCHK

Receive clock check control register

 

0x4400 008C

0x4500 008C

0x4600 008C

REVTCTL

Receiver DMA event control register

 

0x4400 00A0

0x4500 00A0

0x4600 00A0

XGBLCTL

Transmitter global control register. Alias of GBLCTL, only

 

 

 

 

 

transmit bits are affected - allows transmitter to be reset

 

 

 

 

 

independently from receiver

 

0x4400 00A4

0x4500 00A4

0x4600 00A4

XMASK

Transmit format unit bit mask register

 

0x4400 00A8

0x4500 00A8

0x4600 00A8

XFMT

Transmit bit stream format register

 

0x4400 00AC

0x4500 00AC

0x4600 00AC

AFSXCTL

Transmit frame sync control register

 

0x4400 00B0

0x4500 00B0

0x4600 00B0

ACLKXCTL

Transmit clock control register

 

0x4400 00B4

0x4500 00B4

0x4600 00B4

AHCLKXCTL

Transmit high-frequency clock control register

 

0x4400 00B8

0x4500 00B8

0x4600 00B8

XTDM

Transmit TDM time slot 0-31 register

 

0x4400 00BC

0x4500 00BC

0x4600 00BC

XINTCTL

Transmitter interrupt control register

 

0x4400 00C0

0x4500 00C0

0x4600 00C0

XSTAT

Transmitter status register

 

0x4400 00C4

0x4500 00C4

0x4600 00C4

XSLOT

Current transmit TDM time slot register

70

Peripheral and Electrical Specifications

 

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsHardware Features Device CharacteristicsCharacteristics of the C672x Processors C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankProgram Cache Control Registers Cache ModeProgram Cache Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstC672x Memory Map Memory Map SummaryFfff Boot Mode Uhpihcs Boot ModesRequired Boot Pin Settings at Device Reset SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View 12. Terminal Functions Signal Name RFP GDHTerminal Functions ZDHIO/I IPD Description ZDH AFSR0 AHCLKR0/AHCLKR1ACLKR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevelopment Support DevelopmentDevice Support Device Family TMS 320 C6727 GDH a 250Prefix Device Speed Range Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Options for Configuring SPI0, I2C0, and I2C1 Device Configuration RegistersDevice-Level Configuration Registers Peripheral Pin Multiplexing OptionsConfiguration Option Peripheral Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityRecommended Operating Conditions1 Electrical SpecificationsAbsolute Maximum Ratings1 UnitII, IOZ Parameter Test Conditions MIN TYP MAX UnitDvdd GDH, CVParameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Timing Requirements ResetReset Electrical Data/Timing MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationREQ DMAXRAM REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionDMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific InformationEmras ResetDSP Emif EmweEMWEDQM0 EmcasEmclk EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Timing Requirements Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements Uhpi Device-Specific Information 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Major Modes on C672xUhpihasb DSPUHPIHD16/HHWIL Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30CUhpi Peripheral Registers Descriptions 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENAHpiamsb Description BIT no Name Reset Read Value Write318 Reserved Hpiaumb DescriptionUniversal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsRegister Byte Description Name Address Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions McASP Internal RegistersDITCSRA0 XclkchkXevtctl DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN2Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationMaster SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information15.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address Inter-Integrated Circuit I2C Timing 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing 34. I2C Input Timing RequirementsParameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt 36. RTI Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions RTI Internal RegistersRtidwdprld RtiintflagRtidwdctrl RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationBoard Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions EMIPLL Registers Descriptions 41. PLL Controller RegistersSpio CODEC, DIRADC, DAC, DSD RTIADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice
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