Texas Instruments TMS320C6726, TMS320C6727 Emif Asynchronous Interface Timing Requirements1

Page 50

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 4-7. EMIF Asynchronous Interface Timing Requirements(1) (2)

NO.

28tsu(EM_DV-EM_CLKH)A

29th(EM_CLKH-EM_DIV)A

30tsu(EM_CLKH-EM_WAITV)A

31th(EM_CLKH-EM_WAITIV)A

33tw(EM_WAIT)A

34td(EM_WAITD-HOLD)A

35tsu(EM_WAITA-HOLD)A

 

MIN

MAX

UNIT

Input setup time, read data valid on EM_D[31:0] before EM_CLK

5

 

ns

rising

 

 

 

 

Input hold time, read data valid on EM_D[31:0] after EM_CLK rising

2

 

ns

Setup time, EM_WAIT valid before EM_CLK rising edge

5

 

ns

Hold time, EM_WAIT valid after EM_CLK rising edge

0

 

ns

Pulse width of EM_WAIT assertion and deassertion

2E + 5

 

ns

Delay from EM_WAIT sampled deasserted on EM_CLK rising to

 

4E(3)

ns

beginning of HOLD phase

 

 

 

 

Setup before end of STROBE phase (if no extended wait states are

4E(3)

 

 

inserted) by which EM_WAIT must be sampled asserted on

 

ns

EM_CLK rising in order to add extended wait states.(4)

 

 

 

(1)E = SYSCLK3 (EM_CLK) period.

(2)These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

(3)These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge must also be met in order to ensure the EM_WAIT signal is correctly sampled.

(4)In Figure 4-13, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles.

Table 4-8. EMIF Asynchronous Interface Switching Characteristics(1)

NO.

 

PARAMETER

MIN

MAX

UNIT

1

tc(EM_CLK)

Cycle time, EMIF clock EM_CLK

10

 

ns

2

tw(EM_CLK)

Pulse width, high or low, EMIF clock EM_CLK

3

 

ns

17

tdis(EM_CLKH-EM_DHZ)S

Delay time, EM_CLK rising to EM_D[31:0] 3-stated

 

7.7

ns

18

tena(EM_CLKH-EM_DLZ)S

Output hold time, EM_CLK rising to EM_D[31:0] driving

1.15

 

ns

21

td(EM_CLKH-EM_CS2V)A

Delay time, from EM_CLK rising edge to EM_CS[2] valid

0

8

ns

22

td(EM_CLKH-EM_WE_DQMV)A

Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid

0

8

ns

23

td(EM_CLKH-EM_AV)A

Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid

0

8

ns

24

td(EM_CLKH-EM_DV)A

Delay time, EM_CLK rising to EM_D[31:0] valid

0

8

ns

25

td(EM_CLKH-EM_OEV)A

Delay time, EM_CLK rising to EM_OE valid

0

8

ns

26

td(EM_CLKH-EM_RW)A

Delay time, EM_CLK rising to EM_RW valid

0

8

ns

27

tdis(EM_CLKH-EM_DDIS)A

Delay time, EM_CLK rising to EM_D[31:0] 3-stated

0

8

ns

32

td(EM_CLKH-EM_WE)A

Delay time, EM_CLK rising to EM_WE valid

0

8

ns

(1)These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.

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Peripheral and Electrical Specifications

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsHardware Features Device CharacteristicsCharacteristics of the C672x Processors C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankProgram Cache Control Registers Cache ModeProgram Cache Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstFfff Memory Map SummaryC672x Memory Map Boot Mode Uhpihcs Boot ModesRequired Boot Pin Settings at Device Reset SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View 12. Terminal Functions Signal Name RFP GDHTerminal Functions ZDHIO/I IPD Description ZDH AFSR0 AHCLKR0/AHCLKR1ACLKR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevice Support DevelopmentDevelopment Support Device Family TMS 320 C6727 GDH a 250Prefix Device Speed Range Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Options for Configuring SPI0, I2C0, and I2C1 Device Configuration RegistersDevice-Level Configuration Registers Peripheral Pin Multiplexing OptionsConfiguration Option Peripheral Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityRecommended Operating Conditions1 Electrical SpecificationsAbsolute Maximum Ratings1 UnitII, IOZ Parameter Test Conditions MIN TYP MAX UnitDvdd GDH, CVTester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing Reset Timing Requirements ResetReset Electrical Data/Timing MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationREQ DMAXRAM REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionByte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts External Memory Interface Emif Emif Device-Specific InformationEmras ResetDSP Emif EmweEMWEDQM0 EmcasEmclk EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Timing Requirements Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements Uhpi Device-Specific Information 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Major Modes on C672xUhpihasb DSPUHPIHD16/HHWIL Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30CUhpi Peripheral Registers Descriptions 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENAHpiamsb Description BIT no Name Reset Read Value Write318 Reserved Hpiaumb Description15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsRegister Byte Description Name Address Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions McASP Internal RegistersDITCSRA0 XclkchkXevtctl DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN222. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationSlave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific InformationRegister Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions Inter-Integrated Circuit I2C Timing 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing 34. I2C Input Timing RequirementsI2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information 36. RTI Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions RTI Internal RegistersRtidwdprld RtiintflagRtidwdctrl RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationBoard Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions EMIPLL Registers Descriptions 41. PLL Controller RegistersSpio CODEC, DIRADC, DAC, DSD RTIADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice
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