Texas Instruments TMS320C6726 Multichannel Audio Serial Ports McASP0, McASP1, and McASP2, Gio

Page 68

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.13Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

∙Flexible clock and frame sync generation logic and on-chip dividers

∙Up to sixteen transmit or receive data pins and serializers

∙Large number of serial data format options, including:

–TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).

–Time slots of 8,12,16, 20, 24, 28, and 32 bits.

–First bit delay 0, 1, or 2 clocks.

–MSB or LSB first bit order.

–Left- or right-aligned data words within time slots

∙DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.

∙Extensive error-checking and mute generation logic

∙All unused pins GPIO-capable

Peripheral

Configuration

Bus

McASP

DMA Bus (Dedicated)

 

 

Pins

GIO

Receive Logic

AHCLKRx

Clock/Frame Generator

ACLKRx

Control

State Machine

AFSRx

 

 

 

 

Clock Check and

AMUTEINx

DIT RAM

Error Detection

AMUTEx

384 C

 

 

384 U

Transmit Logic

AFSXx

Optional

 

Clock/Frame Generator

ACLKXx

 

State Machine

AHCLKXx

 

 

Transmit

Serializer 0

AXRx[0]

Formatter

 

 

 

Serializer 1

AXRx[1]

Receive

Serializer y

AXRx[y]

Formatter

 

McASPx (x = 0, 1, 2)

 

Function

Receive Master Clock Receive Bit Clock

Receive Left/Right Clock or Frame Sync

The McASPs DO NOT have dedicated AMUTEINx pins.

Transmit Left/Right Clock or Frame Sync Transmit Bit Clock

Transmit Master Clock

Transmit/Receive Serial Data Pin

Transmit/Receive Serial Data Pin

Transmit/Receive Serial Data Pin

Figure 4-25. McASP Block Diagram

68

Peripheral and Electrical Specifications

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsDevice Characteristics Characteristics of the C672x ProcessorsHardware Features C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankCache Mode Program CacheProgram Cache Control Registers Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstFfff Memory Map SummaryC672x Memory Map Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDHIO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevice Support DevelopmentDevelopment Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing OptionsOptions for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityElectrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 UnitParameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CVTester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationDMAX RAMREQ REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionByte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts External Memory Interface Emif Emif Device-Specific InformationReset DSP EmifEmras EmweEmcas EmclkEMWEDQM0 EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672xDSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENABIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb Description15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsDevice-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal RegistersXclkchk XevtctlDITCSRA0 DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN222. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationSlave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific InformationRegister Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing RequirementsI2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal RegistersRtiintflag RtidwdctrlRtidwdprld RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationParameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMIPLL Registers Descriptions 41. PLL Controller RegistersCODEC, DIR ADC, DAC, DSDSpio RTIADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice
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