Texas Instruments TMS320C6726, TMS320C6727, TMS320C6722 warranty BIT no Name Description, PINCAP7

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TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Figure 2-6shows the bit layout of the CFGPIN0 register and Table 2-10contains a description of the bits.

31							8
			Reserved
7	6	5	4	3	2	1	0
PINCAP7	PINCAP6	PINCAP5	PINCAP4	PINCAP3	PINCAP2	PINCAP1	PINCAP0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000)

Table 2-10. CFGPIN0 Register Bit Field Description (0x4000 0000)

BIT NO.	NAME	DESCRIPTION
31:8	Reserved	Reads are indeterminate. Only 0s should be written to these bits.
7	PINCAP7	SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin.
6	PINCAP6	SPI0_SIMO pin state captured on rising edge of RESET pin.
5	PINCAP5	SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin.
4	PINCAP4	SPI0_SCS/I2C1_SCL pin state captured on rising edge of RESET pin.
3	PINCAP3	SPI0_ENA/I2C1_SDA pin state captured on rising edge of RESET pin.
2	PINCAP2	AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin.
1	PINCAP1	AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin.
0	PINCAP0	AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin.

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Contents TMS320C6727, TMS320C6726, TMS320C6722 DSPs FeaturesDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Package Thermal Resistance Characteristics ContentsCharacteristics of the C672x Processors Device CharacteristicsHardware Features C6726CPU Data Paths Enhanced C67x+ CPUNew Floating-Point Instructions for C67x+ CPU CPU Interrupt AssignmentsCPU Interrupt Assignments Instruction FLOATING-POINT Improves OperationByte Bank Internal Program/Data ROM and RAMProgram Cache Cache ModeProgram Cache Control Registers Register Name Byte Address DescriptionBlock Diagram of Crossbar Switch High-Performance Crossbar SwitchLabel Bridge Description Master Clock Target Clock Bus BridgesCsprst BIT no Name Reset Value Read Write DescriptionFfff Memory Map SummaryC672x Memory Map Required Boot Pin Settings at Device Reset Boot ModesBoot Mode Uhpihcs SPI0SIMO SPI0CLKPINCAP7 BIT no Name DescriptionPINCAP15 Pin Maps Pin AssignmentsPin Low-Profile Quad Flatpack RFP Suffix-Top View Terminal Functions Signal Name RFP GDH12. Terminal Functions ZDHIO/I IPD Description ZDH ACLKR0 AHCLKR0/AHCLKR1AFSR0 AHCLKX0/AHCLKX2Power Pins 144-Pin RFP Package Power Pins 256-Terminal GDH/ZDH PackageDevice Support DevelopmentDevelopment Support Prefix Device Speed Range TMS 320 C6727 GDH a 250Device Family Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Device-Level Configuration Registers Device Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing OptionsOptions for Configuring Emif and Uhpi C6727 Only Options for Configuring SPI1, McASP0, and McASP1 Data PinsConfiguration Option Peripheral Peripheral Pin Multiplexing ControlPIN First Priority Second Priority Third Priority Priority of Control of Data Output on Multiplexed PinsAbsolute Maximum Ratings1 Electrical SpecificationsRecommended Operating Conditions1 UnitDvdd Parameter Test Conditions MIN TYP MAX UnitII, IOZ GDH, CVTester Pin Electronics Parameter InformationParameter Information Device-Specific Information Timing Parameter Symbology Power-Supply Decoupling Power SuppliesPower-Supply Sequencing Reset Electrical Data/Timing ResetReset Timing Requirements MIN MAX UnitDMAX Device-Specific Information Dual Data Movement Accelerator dMAXRAM DMAXREQ REQ RAMSubmit Documentation Feedback Event Number Event Acronym Event Description DMAX Peripheral Event Input AssignmentsByte Address Register Name Description DMAX Configuration RegistersDMAX Peripheral Registers Descriptions External Interrupts Emif Device-Specific Information External Memory Interface EmifDSP Emif ResetEmras EmweEmclk EmcasEMWEDQM0 EMWEDQM1Emif Registers Emif Peripheral Registers DescriptionsEmif Electrical Data/Timing Emif Sdram Interface Switching CharacteristicsEmif Sdram Interface Timing Requirements Parameter MIN MAX UnitEmif Asynchronous Interface Timing Requirements1 Emif Asynchronous Interface Switching Characteristics1Basic Sdram Read Operation Basic Sdram Write Operation EmclkEmras Emcas Emwe 10. Asynchronous Read Select Strobe Mode Asynchronous Read WE Strobe Mode12. Asynchronous Write Select Strobe Mode 11. Asynchronous Write WE Strobe Mode13. Emwait Timing Requirements Universal Host-Port Interface Uhpi C6727 Only 10. HPI Access Types Selected by UHPIHCNTL10Uhpi Device-Specific Information Uhpi Major Modes on C672xUHPIHD16/HHWIL DSPUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINTExternal Host MCU AxyC D150 D16 D3117 BE30D 16. Uhpi Multiplexed Host Address/Data Fullword ModeExternal Host MCU A172 AxyA D150 D16 D3117 BE30C 17. Uhpi Non-Multiplexed Host Address/Data Fullword ModeDevice-Level Configuration Registers Controlling Uhpi 11. Uhpi Configuration RegistersUhpi Peripheral Registers Descriptions Uhpi Internal RegistersBytead Full Nmux Pagem ENA BIT no Name Reset Read Description Value Write318 Reserved BIT no Name Reset Read Value WriteHpiamsb Description Hpiaumb Description15. Uhpi Read and Write Timing Requirements1 Uhpi Electrical Data/TimingUniversal Host-Port Interface Uhpi Read and Write Timing 16. Uhpi Read and Write Switching Characteristics1 Valid Read data Write data UHPIHDSxRead Write UHPIHA150 Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a 22. Multiplexed Read Timings Using Uhpihas23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High GIO Multichannel Audio Serial Ports McASP0, McASP1, and McASP2DIT Clock Pins Data Pins Comments 17. McASP Configurations on C672x DSPMcASP Peripheral Registers Descriptions Device-Level Configuration Registers Controlling McASPRegister Byte Description Name Address McASP Internal RegistersXevtctl XclkchkDITCSRA0 DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 Description AMUTEIN0313 Reserved AMUTEIN1 Description AMUTEIN1AMUTEIN2 AMUTEIN222. McASP Timing Requirements1 McASP Electrical Data/TimingMultichannel Audio Serial Port McASP Timing 23. McASP Switching Characteristics1 ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B 29. McASP Input TimingsACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0B 30. McASP Output TimingsSPI Device-Specific Information Serial Peripheral Interface Ports SPI0, SPI1Slave SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOMaster SPI SPI0 SPI1 Register Name Description Byte Address 24. SPIx Configuration RegistersSPI Peripheral Registers Descriptions 25. General Timing Requirements for SPIx Master Modes1 SPI Electrical Data/TimingSerial Peripheral Interface SPI Timing 26. General Timing Requirements for SPIx Slave Modes1 MIN MAX Unit 2P 27. Additional1 SPI Master Timings, 4-Pin Enable Option229. Additional1 SPI Master Timings, 5-Pin Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin 15.1 I2C Device-Specific Information Inter-Integrated Circuit Serial Ports I2C0, I2C1Register Name Description Byte Address 33. I2Cx Configuration Registers15.2 I2C Peripheral Registers Descriptions 15.3 I2C Electrical Data/Timing 35. I2C Switching Characteristics1Inter-Integrated Circuit I2C Timing 34. I2C Input Timing RequirementsI2CxSDA I2CxSCL Stop Start Repeated 35. I2C Switching CharacteristicsParameter Watchdog Key Register Bit Key RTI Interrupt Real-Time Interrupt RTI Timer With Digital Watchdog16.1 RTI/Digital Watchdog Device-Specific Information 16.2 RTI/Digital Watchdog Registers Descriptions Device-Level Configuration Registers Controlling RTI36. RTI Registers RTI Internal RegistersRtidwdctrl RtiintflagRtidwdprld Rtiwdstatus38. Recommended On-Chip Oscillator Components External Clock Input From Oscillator or Clkin Pin39. Clkin Timing Requirements Clock Electrical Data/TimingPLL Device-Specific Information Phase-Locked Loop PLL40. Allowed PLL Operating Conditions Parameter Default Value Allowed Setting or RangeBoard EMI41. PLL Controller Registers PLL Registers DescriptionsADC, DAC, DSD CODEC, DIRSpio RTIADDS/CHANGES/DELETES Thermal Characteristics for RFP Package Package Thermal Resistance CharacteristicsThermal Characteristics for GDH/ZDH Package Standoff Height Standoff HeightPackaging Information PowerPAD PCB FootprintPage Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Page Important Notice