Texas Instruments TMS320C6722 Boot Modes, Required Boot Pin Settings at Device Reset, Uhpi Bytead

Page 16

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

2.8 Boot Modes

The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the state of various device pins at reset, to determine which mode to enter. Note that in practice, only a few pins are used by the software.

CAUTION

Only an externally applied RESET causes the CFGPIN0 and CFGPIN1 registers to recapture their associated pin values. Neither an emulator reset nor a RTI reset causes these registers to update.

The ROM bootmodes include:

∙Parallel Flash on EM_CS[2]

∙SPI0 or I2C1 master mode from serial EEPROM

∙SPI0 or I2C1 slave mode from external MCU

∙UHPI from an external MCU

Table 2-9describes the required boot pin settings at device reset for each bootmode.

Table 2-9. Required Boot Pin Settings at Device Reset

BOOT MODE

UHPI_HCS

SPI0_SOMI

SPI0_SIMO

SPI0_CLK

UHPI

0

BYTEAD(1)

FULL(1)

NMUX(1)

Parallel Flash

1

0

1

0

SPI0 Master

1

0

0

1

SPI0 Slave

1

0

1

1

I2C1 Master

1

1

0

1

I2C1 Slave

1

1

1

1

(1)When UHPI_HCS is 0, the state of the SPI0_SOMI, SPI0_SIMO, and SPI0_CLK pins is copied into the specified bits in the CFGHPI register described in Table 4-12.

Refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual (literature number SPRS277) for details on supported bootmodes and their implementation.

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsDevice Characteristics Characteristics of the C672x ProcessorsHardware Features C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankCache Mode Program CacheProgram Cache Control Registers Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstC672x Memory Map Memory Map SummaryFfff Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDHIO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevelopment Support DevelopmentDevice Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing OptionsOptions for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityElectrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 UnitParameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CVParameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationDMAX RAMREQ REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionDMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific InformationReset DSP EmifEmras EmweEmcas EmclkEMWEDQM0 EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672xDSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENABIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb DescriptionUniversal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsDevice-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal RegistersXclkchk XevtctlDITCSRA0 DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN2Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationMaster SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information15.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing RequirementsParameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal RegistersRtiintflag RtidwdctrlRtidwdprld RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationParameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMIPLL Registers Descriptions 41. PLL Controller RegistersCODEC, DIR ADC, DAC, DSDSpio RTIADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice
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