Texas Instruments TMS320C6727 AHCLKR0/AHCLKR1, ACLKR0, AFSR0, AHCLKX0/AHCLKX2, ACLKX0, AFSX0

Page 24

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Table 2-12. Terminal Functions (continued)

SIGNAL NAME

RFP

GDH/

TYPE (1)

PULL (2)

GPIO (3)

DESCRIPTION

ZDH

 

 

 

 

 

 

 

 

McASP0, McASP1, McASP2, and SPI1 Serial Ports

AHCLKR0/AHCLKR1

143

B3

IO

-

Y

McASP0 and McASP1 Receive Master Clock

ACLKR0

139

A5

IO

-

Y

McASP0 Receive Bit Clock

AFSR0

141

B4

IO

-

Y

McASP0 Receive Frame Sync (L/R Clock)

AHCLKX0/AHCLKX2

2

C2

IO

-

Y

McASP0 and McASP2 Transmit Master Clock(4)

ACLKX0

142

A4

IO

-

Y

McASP0 Transmit Bit Clock

AFSX0

144

A3

IO

-

Y

McASP0 Transmit Frame Sync (L/R Clock)

AMUTE0

3

C1

O

-

Y

McASP0 MUTE Output

AXR0[0]

113

A14

IO

-

Y

McASP0 Serial Data 0

AXR0[1]

115

B13

IO

-

Y

McASP0 Serial Data 1

AXR0[2]

116

A13

IO

-

Y

McASP0 Serial Data 2

AXR0[3]

117

B12

IO

-

Y

McASP0 Serial Data 3

AXR0[4]

119

A12

IO

-

Y

McASP0 Serial Data 4

AXR0[5]/SPI1_SCS

120

B11

IO

-

Y

McASP0 Serial Data 5 or SPI1 Slave Chip Select

AXR0[6]/SPI1_ENA

121

A11

IO

-

Y

McASP0 Serial Data 6 or SPI1 Enable (Ready)

AXR0[7]/SPI1_CLK

122

B10

IO

-

Y

McASP0 Serial Data 7 or SPI1 Serial Clock

AXR0[8]/AXR1[5]/

126

B9

IO

-

Y

McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1

SPI1_SOMI

Data Pin Slave Out Master In

 

 

 

 

 

AXR0[9]/AXR1[4]/

127

A9

IO

-

Y

McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1

SPI1_SIMO

Data Pin Slave In Master Out

 

 

 

 

 

AXR0[10]/AXR1[3]

130

B8

IO

-

Y

McASP0 Serial Data 10 or McASP1 Serial Data 3

AXR0[11]/AXR1[2]

131

A8

IO

-

Y

McASP0 Serial Data 11 or McASP1 Serial Data 2

AXR0[12]/AXR1[1]

134

B7

IO

-

Y

McASP0 Serial Data 12 or McASP1 Serial Data 1

AXR0[13]/AXR1[0]

135

B6

IO

-

Y

McASP0 Serial Data 13 or McASP1 Serial Data 0

AXR0[14]/AXR2[1]

137

A6

IO

-

Y

McASP0 Serial Data 14 or McASP2 Serial Data 1(4)

AXR0[15]/AXR2[0]

138

B5

IO

-

Y

McASP0 Serial Data 15 or McASP2 Serial Data 0(4)

ACLKR1

9

E1

IO

-

Y

McASP1 Receive Bit Clock

AFSR1

12

F1

IO

-

Y

McASP1 Receive Frame Sync (L/R Clock)

AHCLKX1

5

D1

IO

-

Y

McASP1 Transmit Master Clock

ACLKX1

7

E2

IO

-

Y

McASP1 Transmit Bit Clock

AFSX1

11

F2

IO

-

Y

McASP1 Transmit Frame Sync (L/R Clock)

AMUTE1

4

D2

O

-

Y

McASP1 MUTE Output

AHCLKR2

-

C14

IO

IPD

Y

McASP2 Receive Master Clock

ACLKR2

-

C13

IO

IPD

Y

McASP2 Receive Bit Clock

AFSR2

-

C12

IO

IPD

Y

McASP2 Receive Frame Sync (L/R Clock)

ACLKX2

-

D11

IO

IPD

Y

McASP2 Transmit Bit Clock

AFSX2

-

C11

IO

IPD

Y

McASP2 Transmit Frame Sync (L/R Clock)

AMUTE2/HINT

-

D10

O

IPD

Y

McASP2 MUTE Output or UHPI Host Interrupt

 

 

 

SPI0, I2C0, and I2C1 Serial Port Pins

SPI0_SOMI/I2C0_SDA

111

B14

IO

-

Y

SPI0 Data Pin Slave Out Master In or I2C0 Serial Data

SPI0_SIMO

110

B15

IO

-

Y

SPI0 Data Pin Slave In Master Out

SPI0_CLK/I2C0_SCL

108

C16

IO

-

Y

SPI0 Serial Clock or I2C0 Serial Clock

SPI0_SCS/I2C1_SCL

107

C15

IO

-

Y

SPI0 Slave Chip Select or I2C1 Serial Clock

SPI0_ENA/I2C1_SDA

105

D16

IO

-

Y

SPI0 Enable (Ready) or I2C1 Serial Data

(4)McASP2 is not available on the C6722.

24

Device Overview

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsDevice Characteristics Characteristics of the C672x ProcessorsHardware Features C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments New Floating-Point Instructions for C67x+ CPUCPU Interrupt Assignments Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankCache Mode Program CacheProgram Cache Control Registers Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstMemory Map Summary C672x Memory MapFfff Boot Modes Required Boot Pin Settings at Device ResetBoot Mode Uhpihcs SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View Signal Name RFP GDH Terminal Functions12. Terminal Functions ZDHIO/I IPD Description ZDH AHCLKR0/AHCLKR1 ACLKR0AFSR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevelopment Development SupportDevice Support TMS 320 C6727 GDH a 250 Prefix Device Speed RangeDevice Family Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Device Configuration Registers Device-Level Configuration RegistersOptions for Configuring SPI0, I2C0, and I2C1 Peripheral Pin Multiplexing OptionsOptions for Configuring SPI1, McASP0, and McASP1 Data Pins Options for Configuring Emif and Uhpi C6727 OnlyConfiguration Option Peripheral Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityElectrical Specifications Absolute Maximum Ratings1Recommended Operating Conditions1 UnitParameter Test Conditions MIN TYP MAX Unit DvddII, IOZ GDH, CVParameter Information Parameter Information Device-Specific InformationTester Pin Electronics Timing Parameter Symbology Power Supplies Power-Supply SequencingPower-Supply Decoupling Reset Reset Electrical Data/TimingReset Timing Requirements MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationDMAX RAMREQ REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionDMAX Configuration Registers DMAX Peripheral Registers DescriptionsByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific InformationReset DSP EmifEmras EmweEmcas EmclkEMWEDQM0 EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Switching Characteristics Emif Electrical Data/TimingEmif Sdram Interface Timing Requirements Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Basic Sdram Write Operation Emclk Emras Emcas EmweBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements 10. HPI Access Types Selected by UHPIHCNTL10 Universal Host-Port Interface Uhpi C6727 OnlyUhpi Device-Specific Information Uhpi Major Modes on C672xDSP UHPIHD16/HHWILUhpihasb Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30C11. Uhpi Configuration Registers Device-Level Configuration Registers Controlling UhpiUhpi Peripheral Registers Descriptions Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENABIT no Name Reset Read Value Write 318 ReservedHpiamsb Description Hpiaumb DescriptionUhpi Electrical Data/Timing Universal Host-Port Interface Uhpi Read and Write Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 UHPIHDSx Read Write UHPIHA150Valid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsDevice-Level Configuration Registers Controlling McASP McASP Peripheral Registers DescriptionsRegister Byte Description Name Address McASP Internal RegistersXclkchk XevtctlDITCSRA0 DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer AMUTEIN0 313 ReservedAMUTEIN0 Description AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN2McASP Electrical Data/Timing Multichannel Audio Serial Port McASP Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationSPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMO Master SPISlave SPI 24. SPIx Configuration Registers SPI Peripheral Registers DescriptionsSPI0 SPI1 Register Name Description Byte Address SPI Electrical Data/Timing Serial Peripheral Interface SPI Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information33. I2Cx Configuration Registers 15.2 I2C Peripheral Registers DescriptionsRegister Name Description Byte Address 35. I2C Switching Characteristics1 15.3 I2C Electrical Data/TimingInter-Integrated Circuit I2C Timing 34. I2C Input Timing Requirements35. I2C Switching Characteristics ParameterI2CxSDA I2CxSCL Stop Start Repeated Real-Time Interrupt RTI Timer With Digital Watchdog 16.1 RTI/Digital Watchdog Device-Specific InformationWatchdog Key Register Bit Key RTI Interrupt Device-Level Configuration Registers Controlling RTI 16.2 RTI/Digital Watchdog Registers Descriptions36. RTI Registers RTI Internal RegistersRtiintflag RtidwdctrlRtidwdprld RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationParameter Default Value Allowed Setting or Range 40. Allowed PLL Operating ConditionsBoard EMIPLL Registers Descriptions 41. PLL Controller RegistersCODEC, DIR ADC, DAC, DSDSpio RTIADDS/CHANGES/DELETES Package Thermal Resistance Characteristics Thermal Characteristics for GDH/ZDH PackageThermal Characteristics for RFP Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Page Important Notice
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