Texas Instruments TMS320C6726, TMS320C6727 warranty Dsp, UHPIHD16/HHWIL, Uhpihasb, RDY Interrupt

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

www.ti.com

SPRS268E –MAY 2005 –REVISED JANUARY 2007

Figure 4-15illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0'during the first half of access and '1'during the second half.

CAUTION

Unless configured as general-purpose I/O in the UHPI module, UHPI_HD[31:17] and UHPI_HD[16]/HHWIL will be driven as outputs along with UHPI_HD[15:0] when the HPI is read, even though only the lower half-word is used to transfer data. This can be especially problematic for the UHPI_HD[16]/HHWIL pin which should be used as an input in this mode. Therefore, be sure to configure the upper half of the UHPI_HD bus as general-purpose I/O pins. Furthermore, be sure to program the UHPI_HD[16] function as a general-purpose input to avoid a drive conflict with the external host MCU.

In this mode, as well as the Multiplexed Host Address/Data Fullword mode, the UHPI can be made more secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB and CFGHPIAUMB registers. (See Table 4-13and Table 4-14).

The host is responsible for configuring the internal HPIA register whether or not it is being overridden by the device configuration registers CFGHPIAMSB and CFGHPIAUMB.

After the HPIA register has been set, either a single or a group of autoincrementing accesses to HPID may be performed.

The UHPI_HRDY adds wait states to extend the host MCU access until the C672x DSP has completed the desired operation.

The HINT signal is available for the DSP to interrupt the host MCU. The UHPI also includes an interrupt to the DSP core from the host as part of the HPIC register.

DSP

(A)

EM_D[31:16]/UHPI_HA[15:0]

UHPI_HCNTL[1:0]

UHPI_HD[15:0]

UHPI_HD[16]/HHWIL

UHPI_HD[31:17]

UHPI_HAS(B)

UHPI_HBE[1:0](C)

UHPI_HRW

UHPI_HDS[2](G)

UHPI_HDS[1](G)

UHPI_HCS

UHPI_HRDY

AMUTE2/HINT

NC

NC or GPIO

External Host MCU

A[x:y](D)

D[15:0]

A[1](E)

BE[1:0](F)

R/W

WE(G)

RD(G)

CS

RDY

INTERRUPT

A.May be used as EM_D[31:16]

B.Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus.

C.DSP byte enables UHPI_HBE[3:2] are not required in this mode.

D.Two host address lines or host GPIO if address lines are not available.

E.A[1], assuming this address increments from 0 to 1 between two successive 16-bit accesses.

F.Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write-enable pins.

G.Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Tie UHPI_HDS[2] and UHPI_HDS[1] opposite. For more information, see Figure 4-14.

Figure 4-15. UHPI Multiplexed Host Address/Data Half-Word Mode

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