Texas Instruments TMS320C6722, TMS320C6727, TMS320C6726 15.2 I2C Peripheral Registers Descriptions

Page 94

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.15.2 I2C Peripheral Registers Description(s)

Table 4-33is a list of the I2C registers.

Table 4-33. I2Cx Configuration Registers

I2C0

I2C1

REGISTER NAME

DESCRIPTION

BYTE ADDRESS

BYTE ADDRESS

 

 

0x4900 0000

0x4A00 0000

I2COAR

Own Address Register

0x4900 0004

0x4A00 0004

I2CIER

Interrupt Enable Register

0x4900 0008

0x4A00 0008

I2CSTR

Interrupt Status Register

0x4900 000C

0x4A00 000C

I2CCLKL

Clock Low Time Divider Register

0x4900 0010

0x4A00 0010

I2CCLKH

Clock High Time Divider Register

0x4900 0014

0x4A00 0014

I2CCNT

Data Count Register

0x4900 0018

0x4A00 0018

I2CDRR

Data Receive Register

0x4900 001C

0x4A00 001C

I2CSAR

Slave Address Register

0x4900 0020

0x4A00 0020

I2CDXR

Data Transmit Register

0x4900 0024

0x4A00 0024

I2CMDR

Mode Register

0x4900 0028

0x4A00 0028

I2CISR

Interrupt Source Register

0x4900 002C

0x4A00 002C

I2CEMDR

Extended Mode Register

0x4900 0030

0x4A00 0030

I2CPSC

Prescale Register

0x4900 0034

0x4A00 0034

I2CPID1

Peripheral Identification Register 1

0x4900 0038

0x4A00 0038

I2CPID2

Peripheral Identification Register 2

0x4900 0048

0x4A00 0048

I2CPFUNC

Pin Function Register

0x4900 004C

0x4A00 004C

I2CPDIR

Pin Direction Register

0x4900 0050

0x4A00 0050

I2CPDIN

Pin Data Input Register

0x4900 0054

0x4A00 0054

I2CPDOUT

Pin Data Output Register

0x4900 0058

0x4A00 0058

I2CPDSET

Pin Data Set Register

0x4900 005C

0x4A00 005C

I2CPDCLR

Pin Data Clear Register

94

Peripheral and Electrical Specifications

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Contents Features TMS320C6727, TMS320C6726, TMS320C6722 DSPsDescription Submit Documentation Feedback Device Compatibility Functional Block Diagram Contents Package Thermal Resistance CharacteristicsHardware Features Device CharacteristicsCharacteristics of the C672x Processors C6726Enhanced C67x+ CPU CPU Data PathsCPU Interrupt Assignments CPU Interrupt AssignmentsNew Floating-Point Instructions for C67x+ CPU Instruction FLOATING-POINT Improves OperationInternal Program/Data ROM and RAM Byte BankProgram Cache Control Registers Cache ModeProgram Cache Register Name Byte Address DescriptionHigh-Performance Crossbar Switch Block Diagram of Crossbar SwitchBus Bridges Label Bridge Description Master Clock Target ClockBIT no Name Reset Value Read Write Description CsprstC672x Memory Map Memory Map SummaryFfff Boot Mode Uhpihcs Boot ModesRequired Boot Pin Settings at Device Reset SPI0SIMO SPI0CLKBIT no Name Description PINCAP7PINCAP15 Pin Assignments Pin MapsPin Low-Profile Quad Flatpack RFP Suffix-Top View 12. Terminal Functions Signal Name RFP GDHTerminal Functions ZDHIO/I IPD Description ZDH AFSR0 AHCLKR0/AHCLKR1ACLKR0 AHCLKX0/AHCLKX2Power Pins 256-Terminal GDH/ZDH Package Power Pins 144-Pin RFP PackageDevelopment Support DevelopmentDevice Support Device Family TMS 320 C6727 GDH a 250Prefix Device Speed Range Package Type ‡ §Documentation Support C672x devices are documented in the tools v6.0 documentation Options for Configuring SPI0, I2C0, and I2C1 Device Configuration RegistersDevice-Level Configuration Registers Peripheral Pin Multiplexing OptionsConfiguration Option Peripheral Options for Configuring SPI1, McASP0, and McASP1 Data PinsOptions for Configuring Emif and Uhpi C6727 Only Peripheral Pin Multiplexing ControlPriority of Control of Data Output on Multiplexed Pins PIN First Priority Second Priority Third PriorityRecommended Operating Conditions1 Electrical SpecificationsAbsolute Maximum Ratings1 UnitII, IOZ Parameter Test Conditions MIN TYP MAX UnitDvdd GDH, CVParameter Information Device-Specific Information Parameter InformationTester Pin Electronics Timing Parameter Symbology Power-Supply Sequencing Power SuppliesPower-Supply Decoupling Reset Timing Requirements ResetReset Electrical Data/Timing MIN MAX UnitDual Data Movement Accelerator dMAX DMAX Device-Specific InformationREQ DMAXRAM REQ RAMSubmit Documentation Feedback DMAX Peripheral Event Input Assignments Event Number Event Acronym Event DescriptionDMAX Peripheral Registers Descriptions DMAX Configuration RegistersByte Address Register Name Description External Interrupts External Memory Interface Emif Emif Device-Specific InformationEmras ResetDSP Emif EmweEMWEDQM0 EmcasEmclk EMWEDQM1Emif Peripheral Registers Descriptions Emif RegistersEmif Sdram Interface Timing Requirements Emif Sdram Interface Switching CharacteristicsEmif Electrical Data/Timing Parameter MIN MAX UnitEmif Asynchronous Interface Switching Characteristics1 Emif Asynchronous Interface Timing Requirements1Emras Emcas Emwe Basic Sdram Write Operation EmclkBasic Sdram Read Operation Asynchronous Read WE Strobe Mode 10. Asynchronous Read Select Strobe Mode11. Asynchronous Write WE Strobe Mode 12. Asynchronous Write Select Strobe Mode13. Emwait Timing Requirements Uhpi Device-Specific Information 10. HPI Access Types Selected by UHPIHCNTL10Universal Host-Port Interface Uhpi C6727 Only Uhpi Major Modes on C672xUhpihasb DSPUHPIHD16/HHWIL Uhpihrw UHPIHDS2G UHPIHDS1G Uhpihcs Uhpihrdy AMUTE2/HINT16. Uhpi Multiplexed Host Address/Data Fullword Mode External Host MCU AxyC D150 D16 D3117 BE30D17. Uhpi Non-Multiplexed Host Address/Data Fullword Mode External Host MCU A172 AxyA D150 D16 D3117 BE30CUhpi Peripheral Registers Descriptions 11. Uhpi Configuration RegistersDevice-Level Configuration Registers Controlling Uhpi Uhpi Internal RegistersBIT no Name Reset Read Description Value Write Bytead Full Nmux Pagem ENAHpiamsb Description BIT no Name Reset Read Value Write318 Reserved Hpiaumb DescriptionUniversal Host-Port Interface Uhpi Read and Write Timing Uhpi Electrical Data/Timing15. Uhpi Read and Write Timing Requirements1 16. Uhpi Read and Write Switching Characteristics1 Read Write UHPIHA150 UHPIHDSxValid Read data Write data 22. Multiplexed Read Timings Using Uhpihas Uhpihcs Uhpihas UHPIHCNTL10 Uhpihrw Uhpihhwil Hstrobe a23. Multiplexed Read Timings With Uhpihas Held High 24. Multiplexed Write Timings With Uhpihas Held High Multichannel Audio Serial Ports McASP0, McASP1, and McASP2 GIO17. McASP Configurations on C672x DSP DIT Clock Pins Data Pins CommentsRegister Byte Description Name Address Device-Level Configuration Registers Controlling McASPMcASP Peripheral Registers Descriptions McASP Internal RegistersDITCSRA0 XclkchkXevtctl DITCSRA10x4500 020C XBUF3 Transmit buffer register for serializer 313 Reserved AMUTEIN0AMUTEIN0 Description AMUTEIN1 AMUTEIN1 DescriptionAMUTEIN2 AMUTEIN2Multichannel Audio Serial Port McASP Timing McASP Electrical Data/Timing22. McASP Timing Requirements1 23. McASP Switching Characteristics1 29. McASP Input Timings ACLKR/X Clkrp = Clkxp = 0A ACLKR/X Clkrp = Clkxp = 1B30. McASP Output Timings ACLKR/X Clkrp = Clkxp = 1A ACLKR/X Clkrp = Clkxp = 0BSerial Peripheral Interface Ports SPI0, SPI1 SPI Device-Specific InformationMaster SPI SPIxSCS SPIxENA SPIxCLK SPIxSOMI SPIxSIMOSlave SPI SPI Peripheral Registers Descriptions 24. SPIx Configuration RegistersSPI0 SPI1 Register Name Description Byte Address Serial Peripheral Interface SPI Timing SPI Electrical Data/Timing25. General Timing Requirements for SPIx Master Modes1 26. General Timing Requirements for SPIx Slave Modes1 27. Additional1 SPI Master Timings, 4-Pin Enable Option2 MIN MAX Unit 2P29. Additional1 SPI Master Timings, 5-Pin Option2 30. Additional1 SPI Slave Timings, 4-Pin Enable Option2 31. Additional1 SPI Slave Timings, 4-Pin Chip Select Option232. Additional1 SPI Slave Timings, 5-Pin Option2 33. SPI Timings-Master Mode 34. SPI Timings-Slave Mode 35. SPI Timings-Master Mode 4-Pin and 5-Pin 36. SPI Timings-Slave Mode 4-Pin and 5-Pin Inter-Integrated Circuit Serial Ports I2C0, I2C1 15.1 I2C Device-Specific Information15.2 I2C Peripheral Registers Descriptions 33. I2Cx Configuration RegistersRegister Name Description Byte Address Inter-Integrated Circuit I2C Timing 35. I2C Switching Characteristics115.3 I2C Electrical Data/Timing 34. I2C Input Timing RequirementsParameter 35. I2C Switching CharacteristicsI2CxSDA I2CxSCL Stop Start Repeated 16.1 RTI/Digital Watchdog Device-Specific Information Real-Time Interrupt RTI Timer With Digital WatchdogWatchdog Key Register Bit Key RTI Interrupt 36. RTI Registers Device-Level Configuration Registers Controlling RTI16.2 RTI/Digital Watchdog Registers Descriptions RTI Internal RegistersRtidwdprld RtiintflagRtidwdctrl RtiwdstatusExternal Clock Input From Oscillator or Clkin Pin 38. Recommended On-Chip Oscillator ComponentsClock Electrical Data/Timing 39. Clkin Timing RequirementsPhase-Locked Loop PLL PLL Device-Specific InformationBoard Parameter Default Value Allowed Setting or Range40. Allowed PLL Operating Conditions EMIPLL Registers Descriptions 41. PLL Controller RegistersSpio CODEC, DIRADC, DAC, DSD RTIADDS/CHANGES/DELETES Thermal Characteristics for GDH/ZDH Package Package Thermal Resistance CharacteristicsThermal Characteristics for RFP Package Standoff Height Standoff HeightPowerPAD PCB Footprint Packaging InformationPage MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page Page Important Notice
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