Texas Instruments MSC1210 manuals

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Texas Instruments MSC1210 Manual

Texas Instruments MSC1210 Manual

324 pages1.65 Mb

3
9
11
- Chapter 1
13
- This chapter describes the basic function of the MSC1210 analog-to-digital converter (ADC).
- 141.1 MSC1210 Description
  - Figure 11. MSC1210 Block Diagram
- 151.2 MSC1210 Pin-Out
  - Figure 12. Pin Configuration of the MSC1210
  - 16Table 11.Pin Descriptions of the MSC1210
  - 18Table 11 Pin Descriptions of the MSC1210 (Continued)
  - 1.2.1 I/O Ports (P0, P1, P2, and P3)
  - 211.2.2 Oscillator Inputs (XTAL1 and XTAL2)
  - 221.2.3 Reset Line (RST)
  - 1.2.4 Address Latch Enable (ALE)
  - 1.2.5 Program Store Enable (PSEN)
  - 231.2.6 External Access (EA)
- 241.3 Enhanced 8051 Core
  - Figure 13. MSC1210 Timing Compared to Standard 8051 Timing
- 251.4 Family Device Compatibility
- 1.5 Flash Memory
- 1.6 High Performance Analog Functions
- 261.7 High-Performance Peripherals
27
- 282.1 Description
- 2.2 Program Memory
  - Figure 21. MSC1210 Memory Map
  - 29Table 21.Program and Data Memory Size.
  - Table 22.Program and Data Memory Addresses.
- 302.3 Data Memory
  - 2.3.1 On-Chip Extended Static RAM (SRAM)
  - 312.3.2 On-Chip Flash Data Memory
  - 2.3.3 External Data Memory
  - Figure 22. MSC1210 Memory Map Register Bank.
- 322.4 Internal RAM
  - 332.4.1 The Stack
  - 2.4.2 Register Banks
  - 342.4.3 Bit Memory
  - 362.4.4 Special Function Register (SFR) Memory
37 !
- 383.1 Description
  - Table 31.SFR Names and Addresses.
- 393.2 Referencing SFRs
  - 3.2.1 Referencing Bits of SFRs
- 403.3 BitAddressable SFRs
- 3.4 SFR Types
- 413.5 SFR Definitions
51"
- 524.1 Description
- 4.2 Accumulator
- 4.3 R Registers
- 534.4 B Register
- 4.5 Program Counter (PC)
- 544.6 Data Pointer (DPTR0/DPTR1)
- 4.7 Stack Pointer (SP)
55#
- 565.1 Description
  - Table 51.MSC1210 Addressing Modes.
- 5.2 Immediate Addressing
- 575.3 Direct Addressing
- 585.4 Indirect Addressing
- 595.5 External Direct Addressing
- 605.6 External Indirect Addressing
- 5.7 Code Indirect Adressing
61$ %
- 626.1 Description
- 6.2 Conditional Branching
- 6.3 Direct Jumps
- 646.4 Direct Calls
- 6.5 Returns From Routines
- 6.6 Interrupts
65
- 667.1 Description
  - Figure 71. Standard 8051 Timing.
- 687.2 System Timers
  - 707.2.1 Microseconds Timer
  - 7.2.2 Milliseconds Timer
  - 71Figure 74. System Timing Interrupt Control
- 737.3 Startup Timing
  - 74Figure 77. Serial Flash Programming Power-On Timing (EA is ignored)
  - Table 71.Signal Definitions for Reset Timing Diagrams
75
- 768.1 Description
- 8.2 How Does a Timer Count?
- 8.3 Using Timers to Measure Time
  - 8.3.1 How Long Does a Timer Take to Count?
  - 788.3.2 Timer SFRs
  - Table 81.Timer Conrol SFRs.
  - 798.3.3 TMOD SFR
  - 80Table 82.Timer Modes and Usage
  - Figure 81. Timer 0/1 Block Diagram for Modes 0 and 1
  - 81Table 83.Example of 8-Bit Auto-Reload
  - 828.3.4 TCON SFR
  - Table 84.TCON (88H) SFR
  - 838.3.5 Initializing a Timer
  - 8.3.6 Reading the Timer
  - 858.3.7 Timing the Length of Events
- 868.4 Using Timers as Event Counters
- 878.5 Using Timer 2
91
- 929.1 Description
- 939.2 Setting the Serial Port Mode
  - 94Table 91.SM0 and SM1 Function Definitions.
  - 959.2.1 Serial Mode 0: Synchronous Half-Duplex
  - 97Figure 93. Serial Port Mode 1 Transmit Timing.
  - Figure 94. Serial Port 0 Mode 1 Receive Timing.
  - 98Table 92.Common Baud Rates Using Timer 1
  - 99Table 93.Common Baud Rates Using Timer 2
  - 9.2.3 Serial Mode 2: Asynchronous Full-Duplex
  - Figure 95. Serial Port 0 Mode 2 Transmit Timing.
  - 100Figure 96. Serial Port 0 Mode 2 Receive Timing.
  - 1019.2.4 Serial Mode 3: Asynchronous Full-Duplex
  - Figure 97. Serial Port 0 Mode 3 Transmit Timing.
  - Figure 98. Serial Port 0 Mode 3 Receive Timing.
- 1039.3 Setting the Serial Port Baud Rate
  - Table 94.Mode 0 Commonly Used Baud Rates.
  - 104Table 95.Baud Rate Settings for Timer 1.
  - Table 96.Baud Rate Settings for Timer 2.
- 1059.4 Writing to the Serial Port
- 1069.5 Reading the Serial Port
- Chapter 10
107
- Chapter 10 describes the interrupts of the MSC1210 ADC.
- 10810.1 Description
- 10910.2 Events That Can Trigger Interrupts
  - The MSC1210 can be configured so that any of the events in Table 101 will cause an interrupt.
  - Table 101.Interrupt Sources
- 11110.3 Enabling Interrupts
  - Table 102.IE (A8H) SFR
  - Table 103.EICON (D8H) SFR
  - Table 104.EIE (E8H) SFR
- 11210.4 Polling Sequence
- 11310.5 Interrupt Priorities
  - Table 105.IP (B8H) SFR
  - Table 106.EIP (F8H) SFR
- 11410.6 Interrupt Triggering
- 10.7 Exiting Interrupts
- 11510.8 Types of Interrupts
  - 10.8.1 Serial Interrupts
  - 10.8.2 External Interrupts
  - 116Table 107.EXIF (91H) SFR
  - 11710.8.3 Timer Interrupts
  - 10.8.4 Watchdog Interrupt
  - 10.8.5 Auxiliary Interrupts
  - 118Table 108.Clearing Auxiliary Interrupts
  - Table 109.AIE (A6H) SFR
  - 119Table 1010. AISTAT (A7H) SFR
  - Table 1011. PAI (A5H) SFR
  - 120Table 1012. PPI Bits of PAI SFR
- 12110.9 Waking Up from Idle Mode
  - Table 1013. EWU (C6H) SFR
- 12210.10 Register Protection
- 12410.11 Common Problems with Interrupts
125$ & ' (
- 12611.1 Description
  - Figure 111. Block Diagram
- 12711.2 Tone Generator
  - Figure 112. Tone Generator Circuit
  - 12811.2.1 Tone Generator Waveforms
  - Figure 113. Timing Diagram of Tone Generator in Staircase Mode
  - Figure 114. Timing Diagram of Tone Generator in Square Wave Mode
- 12911.3 PWM Generator
  - Table 111.PWM Polarity Conditions
  - 130Figure 115. Timing Diagram of a PWM Waveform
  - 13211.3.1 Example of PWM Tone Generation
  - Table 112.Configuring the PWM for Tone Generation
  - Table 113.Statement Explanations
    - Statement #
  - 13311.3.2 Example of PWM Tone Generation Idling
  - 134Table 114.Configuring the PWM for Tone Generation with PWM Idling
  - Table 115.Statement Explanations
    - Statement #
  - 13511.3.3 Example of Updating PWM
  - Figure 116. PWM Timing
- Chapter 12
137#))* +
- Chapter 12 describes the ADC of the MSC1210.
- 13912.2 Input Multiplexer
  - Figure 122. Input Multiplexer Configuration
- 14112.3 Temperature Sensor
- 14312.4 Burnout Current Sources
- 14412.5 Input Buffer
- 12.6 Analog Input
  - Figure 123. Basic Input Structure of the MSC1210
- 14512.7 Programmable Gain Amplifier (PGA)
  - Table 121.PGA Settings
- 14612.8 Offset DAC
- 12.9 Modulator
- 14712.10 Calibration
  - Table 122.Calibration Mode Control Bits
- 14812.11 Digital Filter
  - Figure 124. Filter Step Responses
  - 15012.11.1 Multiplexing Channels
  - Table 123.Filter Settling
  - Table 124.Output Data Rate and Channel Rate
  - Table 125.Output Data Rate and Channel Rate (10x faster)
- 15112.12 Voltage Reference
- 15212.13 Summation/Shifter Register
  - 15412.13.1 Manual Summation Mode
  - 12.13.2 ADC Summation Mode
  - 15512.13.3 Manual Shift (Divide) Mode
  - 12.13.4 ADC Summation with Shift (Divide) Mode
- 15612.14 Interrupt-Driven ADC Sampling
- 15812.15 Syncronizing Multiple MSC1210 Devices
- 16012.16 Ratiometric Measurements
  - Figure 126. Circuit Drawing
  - 16112.16.1 Differential V
- Chapter 13
163 $ , $!
- Chapter 13 describes the serial peripheral interface (SPI) of the MSC1210 ADC.
- 16413.1 Description
- 13.2 Functional Description
  - Figure 131. SPI block diagram
  - 165Figure 132. SPI Clock/Data Timing
- 16613.3 Clock Phase and Polarity Controls
- 16713.4 SPI Signals
  - 13.4.1 Master In Slave Out
  - 13.4.2 Master Out Slave In
  - 13.4.3 Serial Clock
  - 13.4.4 Slave Select
- 16813.5 SPI System Errors
- 16913.6 Data Transfers
  - Figure 133. SPI Reset State
- 17113.7 FIFO Operation
  - Figure 134. SPI FIFO Operation
- 17213.8 Code Examples
175# -%
- 17714.2.1 Power Supply
- Table 141.Typical Sub-Circuit Current Consumption
- Table 142.Comparator Specification
- Table 143.Band Gap Parameters
- 17814.3 Watchdog Timer
  - Figure 142. System Timing Interrupt Control
  - 14.3.1 Watchdog Timer Hardware Configuration
  - 17914.3.2 Enabling Watchdog Timer
  - 18114.3.3 Resetting the Watchdog Timer
  - 18214.3.4 Disabling Watchdog Timer
  - 14.3.5 Watchdog Timeout/Activation
183#+
- 18415.1 Hardware Configuration
  - 15.1.1 Hardware Configuration Registers
  - 18715.1.2 Hardware Configuration Memory
  - 15.1.3 Accessing Configuration Memory in a User Program
- 18815.2 Advanced Flash Memory
  - 15.2.1 Write Protecting Flash Program Memory
  - 15.2.2 Updating Interrupts with Reset Sector Lock
- 18915.3 Breakpoint Generator
  - 15.3.1 Configuring Breakpoints
  - 19015.3.2 Breakpoint Auxiliary Interrupt
  - 15.3.3 Disabling a Breakpoint
- 19115.4 Power Optimization
- 19215.5 Flash Memory as Data Memory
- 19415.6 Advanced Topics and Other Information
195./0#01
- Chapter 16 describes the 8052 Assembly Language.
- Chapter 16
  - 19616.1 Description
  - 16.2 Syntax
  - 19816.3 Number Bases
  - 16.4 Expressions
  - 19916.5 Operator Precedence
    - Table 161.Order of Precedence for Mathematical Operators
  - 16.6 Characters and Character Strings
  - 20016.7 Changing Program Flow (LJMP, SJMP, AJMP)
  - 20116.8 Subroutines (LCALL, ACALL, RET)
  - 20216.9 Register Assignment (MOV)
    - 2042) Clear the contents of Internal RAM address FFH (more efficient):
  - 20516.10 Incrementing and Decrementing Registers (INC, DEC)
  - 20616.11 Program Loops (DJNZ)
  - 20716.12 Setting, Clearing, and Moving Bits (SETB, CLR, CPL, MOV)
  - 20916.13 Bit-Based Decisions and Branching (JB, JBC, JNB, JC, JNC)
  - 21016.14 Value Comparison (CJNE)
  - 21116.15 Less Than and Greater Than Comparison (CJNE)
  - 21216.16 Zero and Non-Zero Decisions (JZ/JNZ)
  - 16.17 Performing Additions (ADD, ADDC)
  - 21416.18 Performing Subtractions (SUBB)
  - 21516.19 Performing Multiplication (MUL)
  - 21616.20 Performing Division (DIV)
  - 21716.21 Shifting Bits (RR, RRC, RL, RLC)
    - Figure 161. Rotate Operations
  - 21816.22 Bit-Wise Logical Instructions (ANL, ORL, XRL)
    - Table 162.Results of ANL
    - Table 163.Results of ORL
    - Table 164.Results of XRL
  - 22016.23 Exchanging Register Values (XCH)
  - 16.24 Swapping Accumulator Nibbles (SWAP)
  - 16.25 Exchanging Nibbles Between Accumulator and Internal RAM (XCHD)
  - 22116.26 Adjusting Accumulator for BCD Addition (DA)
  - 22216.27 Using the Stack (PUSH/POP)
  - 22416.28 Setting the Data Pointer DPTR (MOV DPTR)
  - 22516.29 Reading and Writing External RAM/Data Memory (MOVX)
  - 22616.30 Reading Code Memory/Tables (MOVC)
  - 22816.31 Using Jump Tables (JMP @A+DPTR)
- Chapter 17
2292
- Chapter 17 describes the Keil simulator and its functions.
- 23017.1 Description
- 23217.2 Timers
  - Figure 171. Timer/Counter 0 Mode 2
  - 23317.2.1 Timer 0 & 1 Example
  - Figure 172. Timer/Counter 0
  - Figure 173. Parallel Port 3 Peripheral
- 23917.3 Timer 2
  - Table 171.Timer/Counter 2 Control Bits
  - Figure 176. Timer/Counter 2
- 24017.4 Watchdog Timer
  - Figure 177. Status of Watchdog Peripheral
  - 24117.4.1 Watchdog Reset Facility Example
- 24417.5 System Timer
- 17.6 Clock Control
- 24517.7 Analog-to-Digital Converter
  - 246Figure 178. AnalogtoDigital Converter Peripheral
  - 247Figure 179. Error Message
- 24817.8 Summation/Shifter
  - Figure 1710. Accumulator/Shifter Peripheral
  - 24917.8.1 ADC/Summation/Shifter Example
- 25817.9 Interrupts
  - Figure 1713. List Box for the Interrupt Peripheral
- 25917.10 Ports
  - Figure 1714. Parallel Port 0 Contents Display Window
  - Figure 1715. Error Message
- 26017.11 Serial Peripheral Interface (SPI)
  - Figure 1716.
  - 26217.11.1 SPI Sample Code
- 26617.12 Vision 2 Debug Program Example
  - 267Figure 1717. Keil Debugger
- 26817.13 Serial Port I/O
- 276A.1 Additional Features in the MSC1210 Compared to 8052
- 280C.1 Description
  - Table C1. Boot ROM Routines
  - 281C.1.1 Note Regarding the put_string Function
    - 8052 Instruction-Set Quick-Reference Guide
    - D-2
- 284D.1 8052 Instruction-Set Quick-Reference Guide
- 286E.1 Description
- 287E.2 8052 Instruction Set
  - ACALL Absolute Call within 2k Block
  - 288ADD, ADDC Add Value, Add Value with Carry
  - 289AJMP Absolute Jump within 2k Block
  - 290ANL Bitwise AND
- 291CJNE
  - CLR Clear Register
  - 292CPL Complement Register
  - DA Decimal Adjust Accumulator
  - 293DEC Decrement Register
  - DIV Divide Accumulator by B
- 294DJNZ
  - 295INC Increment Reister
  - 296JB Jump if Bit Set
  - JBC Jump if Bit Set and Clear Bit
  - JC Jump if Carry Set
  - 297JMP Jump to Data Pointer + Accumulator
  - JNB Jump if Bit Not Set
  - JNC Jump if Carry Not Set
  - 298JNZ Jump if Accumulator Not Zero
  - JZ Jump if Accumulator Zero
  - LCALL Long Call
  - LJMP Long Jump
  - 299MOV Move Memory Into/Out of Accumulator
  - MOV Move Into/Out of Carry Bit
  - 300MOV Move into/out of Internal RAM
  - 301MOV DPTR Move value into DPTR
  - MOVC Move Code Byte to Accumulator
  - MOVX Move Data to/from External RAM
  - 302MUL Multiply Accumulator by B
  - NOP No Operation
  - 303ORL Bitwise OR
  - 304POP Pop Value from Stack
  - PUSH Push Value onto Stack
  - 305RET Return from Subroutine
  - RETI Return from Interrupt
  - RL Rotate Accumulator Left
  - 306RLC Rotate Accumulator Left Through Carry
  - RR Rotate Accumulator Right
  - RRC Rotate Accumulator Right Through Carry
  - SETB Set Bit
  - 307SJMP Short Jump
  - SUBB Subtract from Accumulator with Borrow
  - 308SWAP Subtract Accumulator Nibbles
  - XCH Exchange Bytes
  - XCHD Exchange Digit
  - 309XRL Bitwise Exclusive OR
  - 310UNDEFINED
- 312F.1 Bit Addressable SFRs (alphabetical)
  - Enable Interrupt Control (EICON)
  - Extended Interrupt Enable (EIE)
  - 313Extended Interrupt Priority (EIP)
  - Interrupt Enable (IE)
  - 314INTERRUPT PRIORITY (IP)
  - Port 0 (P0)
  - 315Port 1 (P1)
  - Port 2 (P2)
  - 316Port 3 (P3)
  - 317Program Status Word (PSW)
  - 318Serial Control (SCON)
  - 319Timer Control (TCON)
  - 320Timer 2 Control (T2CON)
- 322G.1 SFR/Address Cross-Reference

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