Texas Instruments MSC1210 manual System Timer, Clock Control

System Timer

17.5 System Timer

The MSC1210 device has many time ticks and an additional clock generator (1MHz) that are derived, and, therefore, synchronized to the system clock. Each time tick and clock generator has a set of registers that specify the value of system clock divisions required to generate it. Some of these registers are accessible through the system timer peripheral windows. The editable XTAL Freq.: window allows you to set the crystal clock frequency. Setting it is just a matter of entering the appropriate value. The ONEUSEC editable text window sets the value of the One Microsecond register. Referring to the Chapter 8, Timers, it is apparent that bit patterns in the fifth, sixth and seventh bit positions are ignored; they have no effect. This is also enforced in this peripheral. The One Millisecond Low and One Millisecond High registers are programmed through or displayed in the editable text windows ONEMSL and ONEMSH, respectively. The One Hundred Millisec- onds register, the Millisecond Timer register and the Seconds Timer register are accessed through the HUNDMS, STIMER and MSTIMER editable text windows. The statuses of the second system timer interrupt status flag and the millisecond system timer interrupt status flag are reflected in the checked or cleared statuses of the SEC and MSEC check boxes, respectively. You can also force a second system timer iterrupt or the millisecond system timer interrupt by toggling either of these check boxes. The SYSTEM clock is turned on or turned off by toggling the SYSTON check box. Please refer to Chapter 8, Timers, for a more compre- hensive discussion of the system timer.

The corresponding time interval for the one microsecond timer, the one millisec- ond timer, and the one hundred milliseconds timer, on the bases of the registered system clock frequency and the values of the pertinent timer registers, are dis- played in the non-editable text windows 1∝s, 1ms and 100ms, respectively.

17.6 Clock Control

The clock frequencies affecting the operations of the device timers, watchdog timers, UARTs and SPI systems depend on the states of the bit pattern of the value written into the Clock Control register (CKCON). The stretch time for the external memory access is also determined by this value. The value of the CKCON register can either be written directly into the associated editable text window, or modified or programmed by toggling the T2M, T1M and T0M check boxes, which program and set the crystal frequency divide-by-12 or divide-by-4 modes for Timers 2, 1 and 0, respectively. This allows the MSC1210 to maintain backward compatibility with the standard 8051 processor. The default setting is the divide-by-12 option. The MOVX stretch can be modified by activating the MOVX Duration (Cycles) window. This causes a display of selectable instruction cycle durations, from which, one must be chosen. Please refer to the section for Timer Control for more detailed information on the Clock Control register bit pattern.

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