Texas Instruments MSC1210 manual Watchdog Reset Facility Example

Watchdog Timer

The non-editable Expire in: display window indicates the amount of time left (in milliseconds) before you must perform either a timed access watchdog reset or a watchdog disable, in order to avoid the watchdog timer initiating a system reset (if watchdog reset is enabled). Note that PDWDT does not enable the watchdog timer reset; it is enabled and disabled by the WDRESET bit in hardware configu- ration register 0 (HCR0). This register is located within the flash memory, there- fore, it is not available for read or write in the execution mode. Refer to the section on flash programming for information on programming HCR0. This SFR is ac- cessed using CADDR and CDATA. The WDRESET bit, when set, would enable the watchdog reset. This implies that upon watchdog timeout, the system auto- matically initiates a processor reset procedure. This also implies that even if the watchdog timer interrupt is enabled, the associated ISR will never be called. In order to be able to access the ISR, the watchdog reset must be disabled. This is achieved by clearing the watchdog reset enable bit. The default state for this bit is logic 1, i.e., watchdog reset enabled. The complete watchdog facility cannot be simulated because the configuration address and data access to the HCR0 is not implemented in this simulator version. However, an example is provided here to show how the watchdog system, with an interrupt facility, would be imple- mented were it possible to modify the WDRESET bit of HCR0.

17.4.1 Watchdog Reset Facility Example

#include ”MSC1210.H”

//unsigned char data irqen_init _at_ 0x7f ; // image of PAI #define FWVer 0x04

#define CONVERT 0

char watchdog_loop;

void init_watchdog ( );

void watchdog_interrupt ( );// interrupt 6;

void setport (void)

{

P3DDRL &= 0xf0;

P3DDRL = 0x07; //P30 input, P31 output

TF2 = CLEAR; T2 = CLEAR;

CKCON = 0x20; // Set timer 2 to clk/4

RCAP2 = 0xffd9; //Set Timer 2 to Generate 57690 bps

//Initialize TH2:TL2 so that next clock generates first Baud Rate pulse THL2=0xffff;

T2CON = 0x34; // Set T2 for Serial0 Tx/Rx baudgen

//SCON: Async mode 1, 8−bit UART, enable rcvr; TI=CLEAR, RI = CLEAR SCON = 0x50;

PCON = 0x80; // Set SMOD0 for 16X baud rate clock

}

void init_watchdog ( )

{

Keil Simulator 17-13