Texas Instruments MSC1210 manual SPI Signals, Master In Slave Out, Master Out Slave, Serial Clock

SPI Signals

13.4 SPI Signals

The following paragraphs contain descriptions of the four SPI signals: master in slave out (MISO), master out slave in (MOSI), serial clock (SCK), and slave select (SS).

The port register for P1.4, P1.5, P1.6 and P1.7 must be set (P1 = FxH) to use the SPI functions. Additionally, the pins must be setup as inputs or outputs us- ing the Port 1 Data Direction register (P1DDRH, AFH). For master operation,

P1DDRH = 75H (drive SS pin), and slave P1DDRH = DFH.

13.4.1 Master In Slave Out

MISO is one of two unidirectional serial data signals. It is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.

13.4.2 Master Out Slave In

The MOSI line is the second of the two unidirectional serial data signals. It is an output from a master device and an input to a slave device. The master de- vice places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data.

13.4.3 Serial Clock

SCK, an input to a slave device, is generated by the master device and syn- chronizes data movement in and out of the device through the MOSI and MISO lines. Master and slave devices are capable of exchanging a byte of informa- tion during a sequence of eight clock cycles.

There are four possible timing relationships that can be chosen by using con- trol bits CPOL and CPHA in the SPI control register (SPICON). Both master and slave devices must operate with the same timing. The SPI clock rate select bits, CLK[2:0], in the SPICON of the master device select the clock rate. In a slave device, CLK [2:0] have no effect on the operation of the SPI.

13.4.4 Slave Select

The SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction.

There is no hardware support for mode fault error detection. For the master to monitor the SS line, it either needs to poll the status of the SS signal or con- nect it to INT0 or INT1, which can generate an interrupt when the line goes low. Due to this, it is reasonable for the master to drive P1.4 as the SS signal for control of the slave devices.

The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should be identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line can be tied to DGND as long as only CPHA = 1 clock mode is used.

Serial Peripheral Interface (SPI) 13-5