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Texas Instruments MSC1210 manual 11. summation/Shifter Peripheral

Models: MSC1210

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Summation/Shifter

Figure 17−11. summation/Shifter Peripheral

Figure 17−12. The ADC Peripheral Mid-Stride a Typical 8-Sample Averaging Block

17-28

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Texas Instruments MSC1210 manual 11. summation/Shifter Peripheral

Contents

User’s Guide Important Notice MSC1210 Memory Organization Introduction to the MSC1210Basic Registers System Timing Addressing ModesSerial Communication Pulse Width Modulator/Tone Generator Analog-to-Digital ConverterSerial Peripheral Interface SPI Additional MSC1210 HardwareAdditional Resource Additional Features in the MSC1210 Compared to Clock Timing DiagramBoot ROM Routines Instruction-Set Quick-Reference GuideSPI/PWM/Flash Write Timing System Timing Interrupt Control 16−1 Pin Descriptions of the MSC1210 14−2 Chapter −1. MSC1210 Block Diagram MSC1210 Description−2. Pin Configuration of the MSC1210 MSC1210 Pin-Out−1. Pin Descriptions of the MSC1210 Pin # Name Description−1 Pin Descriptions of the MSC1210 Pin # Name Description1 I/O Ports P0, P1, P2, and P3 AD7Port Port Oscillator Inputs XTAL1 and XTAL2 Address Latch Enable ALE Reset Line RSTProgram Store Enable Psen External Access EA Enhanced 8051 Core −3. MSC1210 Timing Compared to Standard 8051 TimingFlash Memory Family Device CompatibilityHigh Performance Analog Functions High-Performance Peripherals Description Program Memory Data Memory Internal RAM Description Program Memory−1. Program and Data Memory Size MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5−2. Program and Data Memory Addresses Data MemoryOn-Chip Extended Static RAM Sram On-Chip Flash Data Memory External Data MemoryInternal RAM −2. MSC1210 Memory Map Register BankStack Register BanksBit Memory Or execute Special Function Register SFR Memory Defines the MSC1210 SFRs −1. SFR Names and Addresses SCON0Referencing SFRs Referencing Bits of SFRsBit−Addressable SFRs SFR TypesSFR Definitions SFR Definitions SFR Definitions SFR Definitions Can be generated automatically by the MSC1210 P0DDRL/P0DDRH Port 0 Data Direction Low/High Byte, Addresses GCL/GCM/GCH Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H SFR Definitions SFR Definitions SFR Definitions Describes the basic register functions of the MSC1210 ADC Accumulator RegistersRegister Program Counter PCData Pointer DPTR0/DPTR1 Stack Pointer SPDescribes the various addressing modes of the MSC1210 Immediate Addressing Mode Example−1. MSC1210 Addressing Modes Direct Addressing Indirect Addressing External Direct Addressing Movx A,@DPTR Movx @DPTR,AExternal Indirect Addressing Code Indirect AdressingDescribes the program flow of the MSC1210 ADC Conditional Branching Direct JumpsConsider the example Returns From Routines Direct CallsInterrupts Description System Timers Startup Timing −1. Standard 8051 Timing System Timing System Timers −2. MSC1210 Timing Chain and Clock Control Microseconds Timer Milliseconds Timer−4. System Timing Interrupt Control One Hundred Millisecond Clock Flash Programming Mode Power-On Reset Timing Normal-Mode Power-On Reset TimingStartup Timing Symbol Parameter Min Max Unit PsenDescribes the timers of the MSC1210 ADC Using Timers to Measure Time How Does a Timer Count?How Long Does a Timer Take to Count? Width Width ∝s RD or WR StrobeMovx Duration SYS CLKs At 12MHz −1. Timer Conrol SFRs Timer SFRsSFR Name Description SFR Address Bit Addressable? Tmod SFR Mode−2. Timer Modes and Usage TxM1 TxM0 Timer Description of Timer ModeInstruction −3. Example of 8-Bit Auto-ReloadCycle Tcon SFR Bit Name Bit Address Explanation of Function Timer−4. Tcon 88 H SFR Initializing a Timer Reading the TimerDetecting Timer Overflow Timing the Length of Events Using Timers as Event Counters Using Timer 1 T2CON SFRTimer 2 in Auto-Reload Mode Timer 2 in Capture Mode Timer 2 as a Baud Rate Generator Describes serial communication using the MSC1210 ADC Description Setting the Serial Port Mode Function Length Period−1. SM0 and SM1 Function Definitions ModeSerial Mode 0 Synchronous Half-Duplex High four bits bits 4 through 7 are configuration bits−2. Serial Port Mode 0 Receive Timing-High Speed Operation Serial Mode 1 Asynchronous Full-Duplex−3. Serial Port Mode 1 Transmit Timing −2. Common Baud Rates Using Timer BaudRate + 32 @ Timer1OverflowBaudRate + Timer2Overflow BaudRate + 12 @ 256 * TH1−3. Common Baud Rates Using Timer Serial Mode 2 Asynchronous Full-DuplexRcap 2H Rcap 2L + Baud Rate RCAP2HRCAP2L @ 11.0592MHz f OSC−6. Serial Port 0 Mode 2 Receive Timing BaudRate + 2SMOD @ fOSCSerial Mode 3 Asynchronous Full-Duplex −7. Serial Port 0 Mode 3 Transmit TimingSetting the Serial Port Mode Setting the Serial Port Baud Rate −4. Mode 0 Commonly Used Baud RatesTH1 = 256 − Crystal / 192 / Baud Baud Rate−5. Baud Rate Settings for Timer Desired BaudWriting to the Serial Port −6. Baud Rate Settings for TimerBaud Rate 33MHz clk 25MHz clk 11.0592MHz clk Kb/s Reading the Serial Port Describes the interrupts of the MSC1210 ADC JNB TF0,SKIPTOGGLE Events That Can Trigger Interrupts Interrupt/Event Addr Priority Flag Enable Priority Control−1.Interrupt Sources 10-4 Enabling Interrupts −2.IE A8 H SFR−3.EICON D8 H SFR −4.EIE E8 H SFRPolling Sequence −5.IP B8 H SFR Interrupt Priorities−6.EIP F8 H SFR Interrupt Triggering Exiting InterruptsSerial Interrupts Types of InterruptsExternal Interrupts −7.EXIF 91 H SFR Bit Name Explanation of FunctionWatchdog Interrupt Timer InterruptsAuxiliary Interrupts −9.AIE A6 H SFR −8.Clearing Auxiliary InterruptsAux Interrupt Type Method to Clear Interrupt −11. PAI A5 H SFR −10. Aistat A7 H SFRBit Name Explanation of Function Clear Interrupt −12. PPI Bits of PAI SFR PAIx Bits Explanation of Interrupt/EventWaking Up from Idle Mode −13. EWU C6 H SFRRegister Protection Push PSWPush R0 Error − Invalid instruction Common Problems with Interrupts Tone Generator 11-3 Description 11-2PWM Generator 11-5 −1. Block Diagram Tone Generator ToneFrequency +1−3. Timing Diagram of Tone Generator in Staircase Mode Tone Generator WaveformsPWM Generator −1. PWM Polarity ConditionsDuty Cycle = PWM Period +1 − PWM Duty/PWM Period +1 Condition Duty Cycle−5. Timing Diagram of a PWM Waveform This can be expressed in code as −2. Configuring the PWM for Tone Generation Stmt ‘C’ Source Code Assembly Source CodeExample of PWM Tone Generation −3. Statement ExplanationsExample of PWM Tone Generation Idling −5. Statement Explanations −4. Configuring the PWM for Tone Generation with PWM IdlingExplanation Example of Updating PWM −6. PWM Timing11-12 PGA DAC 12-10−1. MSC1210 Architecture −2. Input Multiplexer Configuration Input MultiplexerPositive Input Negative InputTemperature Sensor 12-6 Burnout Current Sources MSBInput Buffer Analog Input@ 10 ACLKFrequency−1.PGA Settings Programmable Gain Amplifier PGAOffset DAC ModulatorCalibration Mode −2.Calibration Mode Control BitsCalibration Digital Filter −4. Filter Step Responses−5. Filter Frequency Responses Multiplexing Channels −3.Filter Settling−4.Output Data Rate and Channel Rate Samples to Discard FilterVoltage Reference −5.Output Data Rate and Channel Rate 10x fasterSummation/Shifter Register SourceSummation Count Shift Summation CountManual Summation Mode ADC Summation ModeManual Shift Divide Mode ADC Summation with Shift Divide ModeInterrupt-Driven ADC Sampling Analog-to-Digital Converter 12-21 Syncronizing Multiple MSC1210 Devices Analog-to-Digital Converter 12-23 Ratiometric Measurements ADC Result + V REFPT100 ADC Result + R REF @ I OUTDifferential Vref 12-26 Clock Phase and Polarity Controls 13-4 SPI Signals 13-5SPI System Errors 13-6 Description 13-2−1. SPI block diagram Functional Description−2. SPI Clock/Data Timing Clock Phase and Polarity Controls SPI Signals Master In Slave OutMaster Out Slave Serial ClockSPI System Errors −3. SPI Reset State Data Transfers13-8 Fifo Operation −4. SPI Fifo OperationCode Examples SPI Master Transfer in Fifo Mode using Interrupts 13-12 Description 14-2 Watchdog Timer 14-4Low-Voltage Detect 14-2 −1. Brownout Reset and Low-Voltage Detection Low-Voltage DetectPower Supply −2.Comparator Specification−1.Typical Sub-Circuit Current Consumption −3.Band Gap ParametersWatchdog Timer Watchdog Timer Hardware ConfigurationEnabling Watchdog Timer Watchdog Timer Resetting the Watchdog Timer Disabling Watchdog Timer Watchdog Timeout/ActivationHardware Configuration 15-2 Power Optimization 15-9Advanced Flash Memory 15-6 Breakpoint Generator 15-7Hardware Configuration Hardware Configuration RegistersHardware Configuration Register 0 HCR0 DFSEL2/1/0 Amount of Flash Data MemoryHardware Configuration Register 1 HCR1 Hardware Configuration Memory Accessing Configuration Memory in a User ProgramAdvanced Flash Memory Updating Interrupts with Reset Sector LockWrite Protecting Flash Program Memory Configuring Breakpoints Breakpoint GeneratorBreakpoint Auxiliary Interrupt Disabling a BreakpointPower Optimization Flash Memory as Data Memory Advanced Topics 15-11 Advanced Topics and Other Information Describes the 8052 Assembly Language Syntax Label and instruction Number Bases ExpressionsOperator Precedence Characters and Character Strings−1.Order of Precedence for Mathematical Operators Order OperatorChanging Program Flow LJMP, SJMP, Ajmp Ljmp LABEL3Subroutines LCALL, ACALL, RET Register Assignment MOV MOV DestinationRegister,SourceValueMOV R2,R1 Invalid MOV @R0,A Incrementing and Decrementing Registers INC, DEC Program Loops Djnz Setting, Clearing, and Moving Bits SETB, CLR, CPL, MOV 16-14 Bit-Based Decisions and Branching JB, JBC, JNB, JC, JNC Value Comparison Cjne Lcall DebouncekeyLess Than and Greater Than Comparison Cjne Checkless JC AislessZero and Non-Zero Decisions JZ/JNZ Performing Additions ADD, AddcPerforming Additions ADD, Addc Performing Subtractions Subb Performing Multiplication MUL Performing Division DIV Shifting Bits RR, RRC, RL, RLC −1. Rotate OperationsBit-Wise Logical Instructions ANL, ORL, XRL −2.Results of ANL−3.Results of ORL −4.Results of XRLAssembly Language 16-25 Exchanging Register Values XCH Swapping Accumulator Nibbles SwapAdjusting Accumulator for BCD Addition DA Using the Stack PUSH/POP Assembly Language 16-29 Setting the Data Pointer Dptr MOV Dptr Reading and Writing External RAM/Data Memory Movx Reading Code Memory/Tables Movc Lcall SUBSUB INC a Using Jump Tables JMP @A+DPTR Describes the Keil simulator and its functions 17-2 Keil Simulator 17-3 Timers −1. Timer/Counter 0 − ModeTimer 0 & 1 Example −2. Timer/Counter−4. Timer/Counter 1 Mode Keil Simulator 17-7 17-8 Keil Simulator 17-9 17-10 −1.Timer/Counter 2 Control Bits TimerRegister Bit Toggle Box Name −7. Status of Watchdog Peripheral Watchdog Reset Facility Example 17-14 Keil Simulator 17-15 System Timer Clock ControlAnalog-to-Digital Converter −8. Analog−to−Digital Converter Peripheral −9. Error Message Summation/Shifter −10. Accumulator/Shifter Peripheral17.8.1 ADC/Summation/Shifter Example 17-22 Keil Simulator 17-23 17-24 Keil Simulator 17-25 17-26 Keil Simulator 17-27 −11. summation/Shifter Peripheral Keil Simulator 17-29 −13. List Box for the Interrupt Peripheral −14. Parallel Port 0 Contents Display Window PortsSerial Peripheral Interface SPI −16. SPI Peripheral WindowKeil Simulator 17-33 SPI Sample Code Keil Simulator 17-35 Serial Peripheral Interface SPI Keil Simulator 17-37 17.12 ∝Vision 2 Debug Program Example −17. Keil Debugger Serial Port I/O −18. Serial Channel 0 Communication Peripheral 17-42 BaudRate + fOSC Transmit Block Baud Rate ComputationBaudRate + fOSC @ Receive Block Baud Rate Computation −19. Clock Control Peripheral Additional Resource Appendix a TopicAdditional Features in the MSC1210 Compared to Appendix B MSC1210 Timing Chain and Clock Control Diagram Figure B−1. MSC1210 Timing Chain and Clock ControlAppendix C Table C−1. Boot ROM Routines Address Routine Declarations DescriptionBoot ROM Routines Page Appendix D 8052 Instruction-Set Quick-Reference Guide JB bitAddr,relAddr Ajmp pg1AddrAppendix E Description Instruction SetDescription 8052 Instruction Set AcallAbsolute Call within 2k Block Acall codeAddressAdd Value, Add Value with Carry ADD, AddcADD A,operand Absolute Jump within 2k Block AjmpAjmp codeAddress Bitwise ANLANL operand1,operand2 Compare and Jump if Not Equal CLRClear Register Cjne operand1,operand2,reladdrDecimal Adjust Accumulator CPLComplement Register CPL operandDecrementing the value causes it to reset to 255 0xFFH Carry flag is not set when the value rolls over from 0 toDEC register See also INC, SubbDecrement and Jump if Not Zero Djnz register,relAddrIncrement Reister INCINC register Jump if Bit Set JBCJump if Bit Set and Clear Bit Jump if Carry SetJNB JMPJNC Lcall JNZLjmp Not affected See also MOVC, MOVX, XCH, XCHD, PUSH, POP MOV operand1, operand2MOV bit1,bit2 Move into/out of Internal RAM MOVMOV operand1,operand2 Movc MOV DptrMovx MUL Multiply Accumulator by BNOP No OperationBitwise or ORLSyntax ORL operand1,operand2 POP Pop Value from StackPush Push Value onto StackRET Return from SubroutineReti Return from InterruptRRC RLCSetb Sjmp Short JumpSubb Subtract from Accumulator with BorrowXCH SwapXchd XRL Bitwise Exclusive orUndefined Instructions OpCode Bytes Cycles Flags ??? 0xA5Appendix F Enable Interrupt Control Eicon Extended Interrupt Enable EIEEX2-External 2 Interrupt Enable Bit Addressable SFRs alphabeticalInterrupt Enable IE Extended Interrupt Priority EIPInterrupt Priority IP Port 0 P0Port 1 P1 Port 2 P2Port 3 P3 Program Status Word PSW Register Bank Register Bank AddressesSerial Mode Description Baud Serial Control SconTimer Control Tcon TconTimer 2 Control T2CON T2CONAppendix G SFR/Address Cross-Reference SFR Name Description SFR Address HexSFRs/Address Cross-Reference Guide alphabetical Spircon