Data Transfers, 3. SPI Reset State | Texas Instruments MSC1210

Data Transfers

13.6 Data Transfers

The transmitted and received data for SPI transfers are both double-buffered. This means that a second byte can be written for transmit before the first byte has been sent. Data that is received does not have to be read from the SPIDAT register until just before the next byte is received. The size of this buffer can essentially be extended with the FIFO mode. This adds from 2 to 128 bytes of FIFO memory.

The FIFO mode uses a portion of the internal indirect RAM from 80H to FFH. The start and end of the FIFO portion of memory is set with the SPISTRT (9EH) and SPIEND (9FH) registers. The only restriction on those addresses is that the value of SPIEND must be larger than SPISTRT. The most significant bit is forced to a one.

There is no signal that switches the SPI interface on or off. It can be powered down using the PDCON (F1H) register. However, if it is powered up, then it is operational. For the master, all that is necessary to transmit a byte is to write the value to SPIDATA (9BH). The SS pin is not used in master mode. It can be

used to drive an SS signal. For slave operation, the bytes will not transfer until SS is asserted and the clock signals are received.

For slave mode, if the SS signal goes high while a byte is being received, that byte is immediately flagged as completed and the interface is prepared for a new byte.

The SPICON (9AH) register controls the SCLK frequency for master operation, and has bits to enable the FIFO, master mode, set bit order, clock polarity and phase. Any change to the SPICON register resets the SPI interface, and clears the counters and pointers, as shown in Figure 13−3.

Figure 13−3. SPI Reset State

Serial Peripheral Interface (SPI)	13-7

Image 169

Texas Instruments MSC1210 manual Data Transfers, 3. SPI Reset State

Contents

User’s Guide Important Notice MSC1210 Memory Organization Introduction to the MSC1210Basic Registers System Timing Addressing ModesSerial Communication Analog-to-Digital Converter Pulse Width Modulator/Tone Generator Additional MSC1210 Hardware Serial Peripheral Interface SPI Additional Resource Clock Timing Diagram Additional Features in the MSC1210 Compared toBoot ROM Routines Instruction-Set Quick-Reference Guide SPI/PWM/Flash Write Timing System Timing Interrupt Control 16−1 Pin Descriptions of the MSC1210 14−2 Chapter MSC1210 Description −1. MSC1210 Block Diagram MSC1210 Pin-Out −2. Pin Configuration of the MSC1210 Pin # Name Description −1. Pin Descriptions of the MSC1210 Pin # Name Description −1 Pin Descriptions of the MSC1210 AD7 1 I/O Ports P0, P1, P2, and P3 Port Port Oscillator Inputs XTAL1 and XTAL2 Address Latch Enable ALE Reset Line RSTProgram Store Enable Psen External Access EA −3. MSC1210 Timing Compared to Standard 8051 Timing Enhanced 8051 Core Flash Memory Family Device CompatibilityHigh Performance Analog Functions High-Performance Peripherals Description Program Memory Data Memory Internal RAM Program Memory Description MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 −1. Program and Data Memory Size −2. Program and Data Memory Addresses Data MemoryOn-Chip Extended Static RAM Sram External Data Memory On-Chip Flash Data Memory −2. MSC1210 Memory Map Register Bank Internal RAM Register Banks Stack Bit Memory Or execute Special Function Register SFR Memory Defines the MSC1210 SFRs SCON0 −1. SFR Names and Addresses Referencing Bits of SFRs Referencing SFRs SFR Types Bit−Addressable SFRs SFR Definitions SFR Definitions SFR Definitions SFR Definitions Can be generated automatically by the MSC1210 P0DDRL/P0DDRH Port 0 Data Direction Low/High Byte, Addresses GCL/GCM/GCH Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H SFR Definitions SFR Definitions SFR Definitions Describes the basic register functions of the MSC1210 ADC Registers Accumulator Program Counter PC Register Stack Pointer SP Data Pointer DPTR0/DPTR1 Describes the various addressing modes of the MSC1210 Immediate Addressing Mode Example−1. MSC1210 Addressing Modes Direct Addressing Indirect Addressing Movx A,@DPTR Movx @DPTR,A External Direct Addressing Code Indirect Adressing External Indirect Addressing Describes the program flow of the MSC1210 ADC Direct Jumps Conditional Branching Consider the example Returns From Routines Direct CallsInterrupts Description System Timers Startup Timing −1. Standard 8051 Timing System Timing System Timers −2. MSC1210 Timing Chain and Clock Control Milliseconds Timer Microseconds Timer −4. System Timing Interrupt Control One Hundred Millisecond Clock Flash Programming Mode Power-On Reset Timing Normal-Mode Power-On Reset TimingStartup Timing Psen Symbol Parameter Min Max Unit Describes the timers of the MSC1210 ADC Using Timers to Measure Time How Does a Timer Count?How Long Does a Timer Take to Count? Width Width ∝s RD or WR StrobeMovx Duration SYS CLKs At 12MHz −1. Timer Conrol SFRs Timer SFRsSFR Name Description SFR Address Bit Addressable? Mode Tmod SFR TxM1 TxM0 Timer Description of Timer Mode −2. Timer Modes and Usage Instruction −3. Example of 8-Bit Auto-ReloadCycle Tcon SFR Bit Name Bit Address Explanation of Function Timer−4. Tcon 88 H SFR Reading the Timer Initializing a Timer Detecting Timer Overflow Timing the Length of Events Using Timers as Event Counters 1 T2CON SFR Using Timer Timer 2 in Auto-Reload Mode Timer 2 in Capture Mode Timer 2 as a Baud Rate Generator Describes serial communication using the MSC1210 ADC Description Function Length Period Setting the Serial Port Mode Mode −1. SM0 and SM1 Function Definitions High four bits bits 4 through 7 are configuration bits Serial Mode 0 Synchronous Half-Duplex Serial Mode 1 Asynchronous Full-Duplex −2. Serial Port Mode 0 Receive Timing-High Speed Operation −3. Serial Port Mode 1 Transmit Timing BaudRate + 32 @ Timer1Overflow −2. Common Baud Rates Using TimerBaudRate + Timer2Overflow BaudRate + 12 @ 256 * TH1 Serial Mode 2 Asynchronous Full-Duplex −3. Common Baud Rates Using TimerRcap 2H Rcap 2L + Baud Rate RCAP2HRCAP2L @ 11.0592MHz f OSC BaudRate + 2SMOD @ fOSC −6. Serial Port 0 Mode 2 Receive Timing −7. Serial Port 0 Mode 3 Transmit Timing Serial Mode 3 Asynchronous Full-Duplex Setting the Serial Port Mode −4. Mode 0 Commonly Used Baud Rates Setting the Serial Port Baud RateTH1 = 256 − Crystal / 192 / Baud Baud Rate Desired Baud −5. Baud Rate Settings for Timer Writing to the Serial Port −6. Baud Rate Settings for TimerBaud Rate 33MHz clk 25MHz clk 11.0592MHz clk Kb/s Reading the Serial Port Describes the interrupts of the MSC1210 ADC JNB TF0,SKIPTOGGLE Events That Can Trigger Interrupts Interrupt/Event Addr Priority Flag Enable Priority Control−1.Interrupt Sources 10-4 −2.IE A8 H SFR Enabling Interrupts−3.EICON D8 H SFR −4.EIE E8 H SFR Polling Sequence −5.IP B8 H SFR Interrupt Priorities−6.EIP F8 H SFR Exiting Interrupts Interrupt Triggering Serial Interrupts Types of InterruptsExternal Interrupts Bit Name Explanation of Function −7.EXIF 91 H SFR Watchdog Interrupt Timer InterruptsAuxiliary Interrupts −9.AIE A6 H SFR −8.Clearing Auxiliary InterruptsAux Interrupt Type Method to Clear Interrupt −11. PAI A5 H SFR −10. Aistat A7 H SFRBit Name Explanation of Function Clear Interrupt PAIx Bits Explanation of Interrupt/Event −12. PPI Bits of PAI SFR −13. EWU C6 H SFR Waking Up from Idle Mode Push PSW Register Protection Push R0 Error − Invalid instruction Common Problems with Interrupts Tone Generator 11-3 Description 11-2PWM Generator 11-5 −1. Block Diagram ToneFrequency +1 Tone Generator Tone Generator Waveforms −3. Timing Diagram of Tone Generator in Staircase Mode −1. PWM Polarity Conditions PWM GeneratorDuty Cycle = PWM Period +1 − PWM Duty/PWM Period +1 Condition Duty Cycle −5. Timing Diagram of a PWM Waveform This can be expressed in code as Stmt ‘C’ Source Code Assembly Source Code −2. Configuring the PWM for Tone GenerationExample of PWM Tone Generation −3. Statement Explanations Example of PWM Tone Generation Idling −5. Statement Explanations −4. Configuring the PWM for Tone Generation with PWM IdlingExplanation −6. PWM Timing Example of Updating PWM 11-12 12-10 PGA DAC −1. MSC1210 Architecture Input Multiplexer −2. Input Multiplexer Configuration Negative Input Positive Input Temperature Sensor 12-6 MSB Burnout Current Sources Analog Input Input Buffer@ 10 ACLKFrequency Programmable Gain Amplifier PGA −1.PGA Settings Modulator Offset DAC Calibration Mode −2.Calibration Mode Control BitsCalibration −4. Filter Step Responses Digital Filter −5. Filter Frequency Responses −3.Filter Settling Multiplexing Channels−4.Output Data Rate and Channel Rate Samples to Discard Filter −5.Output Data Rate and Channel Rate 10x faster Voltage Reference Source Summation/Shifter Register Shift Summation Count Summation Count ADC Summation Mode Manual Summation Mode ADC Summation with Shift Divide Mode Manual Shift Divide Mode Interrupt-Driven ADC Sampling Analog-to-Digital Converter 12-21 Syncronizing Multiple MSC1210 Devices Analog-to-Digital Converter 12-23 ADC Result + V REF Ratiometric MeasurementsPT100 ADC Result + R REF @ I OUT Differential Vref 12-26 SPI Signals 13-5 Clock Phase and Polarity Controls 13-4SPI System Errors 13-6 Description 13-2 Functional Description −1. SPI block diagram −2. SPI Clock/Data Timing Clock Phase and Polarity Controls Master In Slave Out SPI SignalsMaster Out Slave Serial Clock SPI System Errors Data Transfers −3. SPI Reset State 13-8 −4. SPI Fifo Operation Fifo Operation Code Examples SPI Master Transfer in Fifo Mode using Interrupts 13-12 Description 14-2 Watchdog Timer 14-4Low-Voltage Detect 14-2 Low-Voltage Detect −1. Brownout Reset and Low-Voltage Detection −2.Comparator Specification Power Supply−1.Typical Sub-Circuit Current Consumption −3.Band Gap Parameters Watchdog Timer Hardware Configuration Watchdog Timer Enabling Watchdog Timer Watchdog Timer Resetting the Watchdog Timer Watchdog Timeout/Activation Disabling Watchdog Timer Power Optimization 15-9 Hardware Configuration 15-2Advanced Flash Memory 15-6 Breakpoint Generator 15-7 Hardware Configuration Registers Hardware Configuration DFSEL2/1/0 Amount of Flash Data Memory Hardware Configuration Register 0 HCR0 Hardware Configuration Register 1 HCR1 Accessing Configuration Memory in a User Program Hardware Configuration Memory Advanced Flash Memory Updating Interrupts with Reset Sector LockWrite Protecting Flash Program Memory Breakpoint Generator Configuring Breakpoints Disabling a Breakpoint Breakpoint Auxiliary Interrupt Power Optimization Flash Memory as Data Memory Advanced Topics 15-11 Advanced Topics and Other Information Describes the 8052 Assembly Language Syntax Label and instruction Expressions Number Bases Characters and Character Strings Operator Precedence−1.Order of Precedence for Mathematical Operators Order Operator Ljmp LABEL3 Changing Program Flow LJMP, SJMP, Ajmp Subroutines LCALL, ACALL, RET MOV DestinationRegister,SourceValue Register Assignment MOV MOV R2,R1 Invalid MOV @R0,A Incrementing and Decrementing Registers INC, DEC Program Loops Djnz Setting, Clearing, and Moving Bits SETB, CLR, CPL, MOV 16-14 Bit-Based Decisions and Branching JB, JBC, JNB, JC, JNC Lcall Debouncekey Value Comparison Cjne Checkless JC Aisless Less Than and Greater Than Comparison Cjne Performing Additions ADD, Addc Zero and Non-Zero Decisions JZ/JNZ Performing Additions ADD, Addc Performing Subtractions Subb Performing Multiplication MUL Performing Division DIV −1. Rotate Operations Shifting Bits RR, RRC, RL, RLC −2.Results of ANL Bit-Wise Logical Instructions ANL, ORL, XRL−3.Results of ORL −4.Results of XRL Assembly Language 16-25 Swapping Accumulator Nibbles Swap Exchanging Register Values XCH Adjusting Accumulator for BCD Addition DA Using the Stack PUSH/POP Assembly Language 16-29 Setting the Data Pointer Dptr MOV Dptr Reading and Writing External RAM/Data Memory Movx Lcall SUB Reading Code Memory/Tables Movc SUB INC a Using Jump Tables JMP @A+DPTR Describes the Keil simulator and its functions 17-2 Keil Simulator 17-3 −1. Timer/Counter 0 − Mode Timers −2. Timer/Counter Timer 0 & 1 Example −4. Timer/Counter 1 Mode Keil Simulator 17-7 17-8 Keil Simulator 17-9 17-10 −1.Timer/Counter 2 Control Bits TimerRegister Bit Toggle Box Name −7. Status of Watchdog Peripheral Watchdog Reset Facility Example 17-14 Keil Simulator 17-15 Clock Control System Timer Analog-to-Digital Converter −8. Analog−to−Digital Converter Peripheral −9. Error Message −10. Accumulator/Shifter Peripheral Summation/Shifter 17.8.1 ADC/Summation/Shifter Example 17-22 Keil Simulator 17-23 17-24 Keil Simulator 17-25 17-26 Keil Simulator 17-27 −11. summation/Shifter Peripheral Keil Simulator 17-29 −13. List Box for the Interrupt Peripheral Ports −14. Parallel Port 0 Contents Display Window −16. SPI Peripheral Window Serial Peripheral Interface SPI Keil Simulator 17-33 SPI Sample Code Keil Simulator 17-35 Serial Peripheral Interface SPI Keil Simulator 17-37 17.12 ∝Vision 2 Debug Program Example −17. Keil Debugger Serial Port I/O −18. Serial Channel 0 Communication Peripheral 17-42 BaudRate + fOSC Transmit Block Baud Rate ComputationBaudRate + fOSC @ Receive Block Baud Rate Computation −19. Clock Control Peripheral Additional Resource Topic Appendix a Additional Features in the MSC1210 Compared to Appendix B Figure B−1. MSC1210 Timing Chain and Clock Control MSC1210 Timing Chain and Clock Control Diagram Appendix C Address Routine Declarations Description Table C−1. Boot ROM Routines Boot ROM Routines Page Appendix D JB bitAddr,relAddr Ajmp pg1Addr 8052 Instruction-Set Quick-Reference Guide Description Instruction Set Appendix E Description Acall 8052 Instruction SetAbsolute Call within 2k Block Acall codeAddress Add Value, Add Value with Carry ADD, AddcADD A,operand Absolute Jump within 2k Block AjmpAjmp codeAddress Bitwise ANLANL operand1,operand2 CLR Compare and Jump if Not EqualClear Register Cjne operand1,operand2,reladdr CPL Decimal Adjust AccumulatorComplement Register CPL operand Carry flag is not set when the value rolls over from 0 to Decrementing the value causes it to reset to 255 0xFFHDEC register See also INC, Subb Djnz register,relAddr Decrement and Jump if Not Zero Increment Reister INCINC register JBC Jump if Bit SetJump if Bit Set and Clear Bit Jump if Carry Set JNB JMPJNC Lcall JNZLjmp Not affected See also MOVC, MOVX, XCH, XCHD, PUSH, POP MOV operand1, operand2MOV bit1,bit2 Move into/out of Internal RAM MOVMOV operand1,operand2 Movc MOV DptrMovx Multiply Accumulator by B MULNOP No Operation Bitwise or ORLSyntax ORL operand1,operand2 Pop Value from Stack POPPush Push Value onto Stack Return from Subroutine RETReti Return from Interrupt RRC RLCSetb Short Jump SjmpSubb Subtract from Accumulator with Borrow XCH SwapXchd Bitwise Exclusive or XRL Instructions OpCode Bytes Cycles Flags ??? 0xA5 Undefined Appendix F Extended Interrupt Enable EIE Enable Interrupt Control EiconEX2-External 2 Interrupt Enable Bit Addressable SFRs alphabetical Extended Interrupt Priority EIP Interrupt Enable IE Port 0 P0 Interrupt Priority IP Port 2 P2 Port 1 P1 Port 3 P3 Register Bank Register Bank Addresses Program Status Word PSW Serial Control Scon Serial Mode Description Baud Tcon Timer Control Tcon T2CON Timer 2 Control T2CON Appendix G SFR Name Description SFR Address Hex SFR/Address Cross-Reference SFRs/Address Cross-Reference Guide alphabetical Spircon