Texas Instruments MSC1210 manual 12. PPI Bits of PAI SFR, PAIx Bits Explanation of Interrupt/Event

Types of Interrupts

The four bits, PAI0 through PAI3, make up a 4-bit value that indicates the auxil- iary interrupt that triggered the actual interrupt. Because the value returned by PAI is between 0 and 8, it can be used as an index or offset to determine what ISR to execute. There is no priority to the aquxiliary interrupts, but there is a priority to how they are displayed in the PAI register.

Table 10−12. PPI Bits of PAI SFR

	PAIx BITS				Explanation of Interrupt/Event
3		2	1	0
0		0	0	0	No pending peripheral IRQ
0		0	0	1	Digital low-voltage/breakpoint IRQ or lower priority IRQ pending
0		0	1	0	Analog low-voltage IRQ or lower priority IRQ pending
0		0	1	1	SPI receive IRQ or lower priority IRQ pending
0		1	0	0	SPI transmit IRQ or lower priority IRQ pending
0		1	0	1	One millisecond system timer IRQ or lower priority IRQ pending
0		1	1	0	ADC conversion IRQ or lower priority IRQ pending
0		1	1	1	Accumulator IRQ or lower priority IRQ pending
1		0	0	0	One second system timer IRQ pending

10.8.5.1 Low-Voltage Detect Interrupts

There are two low-voltage detect interrupts: one for AVDD and one for DVDD. In addition to these, a voltage level can be selected during programming that will cause a reset. The voltage level used for the interrupts is selected by the Low Voltage Detect control register LVDCON (E7H). If VDD drops below the level se- lected, an interrupt will result (if enabled).

The breakpoint and these two interrupts have priority for encoding in the PAI SFR for the AI interrupt. The detection level can be adjusted from 2.7V to 4.7V or an external analog signal.

Note:

The EAI bit enables the AI Interrupt. This bit is not subject to the global inter- rupt enable (EA). The low-voltage detect interrupts are a level-sensitive in- terrupt and remains set as long as VDD remains below the select voltage.

10.8.5.2 SPI Receive/Transmit Interrupts

The SPI receive or transmit interrupt will be triggered when the number of bytes indicated by SPIRCON have been received, or the number of bytes indicated by SPITCON have been transmitted.

10.8.5.3 Milliseconds/Seconds Interrupts

The MSC1210 includes two additional timer interrupts that may trigger an in- terrupt at regular intervals.

The milliseconds interrupt is triggered every n milliseconds, where n is the number of stored in the MSINT (FAH) SFR. For example, if MSINT is set to 20,

10-14