Texas Instruments MSC1210 manual Timer Interrupts, Watchdog Interrupt, Auxiliary Interrupts

Types of Interrupts

10.8.3 Timer Interrupts

The MSC1210 microcontroller incorporates three 16-bit programmable tim- ers, each of which can generate an interrupt. In addition, there are three other sources for timer interrupts: the milliseconds timer, seconds timer, and watch- dog timer. Each timer has an independent interrupt enable, flag, vector, and priority.

Timers 0, 1, and 2 set their respective flags when their individual timer over- flows. These flags will be set regardless of the interrupt enable status. If the interrupt is enabled, this event will also cause the processor to vector into the corresponding ISR routine, provided it has the highest priority. For Timers 0 and 1, the flags are cleared when the processor jumps to the interrupt vector. Thus, these flags are not available for use by the ISR, but are available outside of the ISR and in applications that do not acknowledge the interrupt (i.e., jump to the vector). If the interrupt is not acknowledged, then software must manual- ly clear the flag bit. In Timer 2, jumping to the interrupt vector does not clear the flag, therefore, software must always clear it manually. Timer 0 and 1 flag bits reside in the TCON register. The Timer 2 flag bit resides in the T2CON reg- ister. The interrupt enables and priorities for Timers 0, 1, and 2 reside in the IE and IP registers, respectively.

10.8.4 Watchdog Interrupt

The watchdog interrupt usually has a different connotation than the timer inter- rupts. Unless the watchdog is being used as a very long timer, the completion of the watchdog count means the software has failed to reset the counter and may be lost. Like other sources, the watchdog timer has a flag bit, an enable, and a priority. It also has its own vector. These are summarized in Table 10−1. For the watchdog timer to perform the processor reset function, it must be en- abled in the flash configuration register during serial or parallel programming.

10.8.5 Auxiliary Interrupts

The auxiliary interrupt allows the MSC1210 to offer additional interrupts without requiring additional ISR vectors. A number of distinct interrupts, when enabled, all provoke the auxiliary interrupt. The ISR then examines the flags to determine which auxiliary interrupt was the source of the interrupt.

The auxiliary interrupt has the highest priority, which means all of the interrupts that are handled by the auxiliary interrupt will always have precedence over non-auxiliary interrupts. Although the interrupt may be disabled if required, the priority level (highest) cannot be altered by the user.

Before returning from the ISR for an auxiliary interrupt, the interrupt source must be cleared and then EICON.4 (AI) must be cleared. The interrupt sources are cleared as shown in Table 10−8.

Interrupts 10-11