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Texas Instruments MSC1210 manual Setting the Serial Port Mode, Function Length Period

Models: MSC1210

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Setting the Serial Port Mode

9.2 Setting the Serial Port Mode

The first thing to be done when using the MSC1210 integrated serial port is, ob- viously, to configure it. This lets you tell the MSC1210 how many data bits are needed, the baud rate to be used, and how the baud rate will be determined.

First, the Serial Control 0 (SCON0) SFR is presented and what each bit of the SFR represents is defined. Remember, SCON1 has the exact same function but relates to the secondary UART.

The individual bits of SCON0 have the following functions:

	7	6	5	4	3	2	1	0	Reset Value

SFR 98H	SM0_0	SM1_0	SM2_0	REN_0	TB8_0	RB8_0	TI_0	RI_0	00H

SM0−2 (bits 7−5)— Serial Port 0 Mode. These bits control the mode of Serial Port 0. Modes 1, 2, and 3 have one start and one stop bit in addition to the eight or nine data bits.

Mode	SM0		SM1	SM2	Function	Length		Period

0	0		0	0	Synchronous	8 bits		12 pCLK(1)
0	0		0	1	Synchronous	8 bits		4 pCLK(1)
1	0		1	x	Asynchronous	10 bits	Timer 1 or 2 baud rate
								equation

2	1		0	0	Asynchronous	11 bits	64 p	(1)	(SMOD = 0)
							CLK
							32 p	(1)	(SMOD = 1)
							CLK
2	1		0	1	Asynchronous	11 bits	64 p	(1)	(SMOD = 0)
							CLK
					with		32 p	(1)	(SMOD = 1)
					multiprocessor		CLK
					multiprocessor
					communication

3	1		1	0	Asynchronous	11 bits	Timer 1 or 2 baud rate
								equation

3	1		1	1	Asynchronous	11 bits	Timer 1 or 2 baud rate
					with			equation
					multiprocessor
					communication

Notes:	1)	pCLK will be equal to tCLK, except that pCLK will stop for IDLE.

REN_0 (bit 4)— Receive Enable. This bit enables/disables the Serial Port 0 received shift register.

0:Serial Port 0 reception disabled.

1:Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous re- ception (mode 0).

TB8_0 (bit 3)— Ninth Transmission Bit State. This bit defines the state of the ninth transmission bit in Serial Port 0 modes 2 and 3.

RB8_0 (bit 2)— Ninth Received Bit State. This bit identifies the state of the ninth reception bit of received data in Serial Port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0.

Serial Communication	9-3

Image 93

Texas Instruments MSC1210 manual Setting the Serial Port Mode, Function Length Period

Contents

User’s Guide Important Notice Introduction to the MSC1210 MSC1210 Memory OrganizationBasic Registers Addressing Modes System TimingSerial Communication Analog-to-Digital Converter Pulse Width Modulator/Tone GeneratorAdditional MSC1210 Hardware Serial Peripheral Interface SPIAdditional Resource Clock Timing Diagram Additional Features in the MSC1210 Compared toBoot ROM Routines Instruction-Set Quick-Reference GuideSPI/PWM/Flash Write Timing System Timing Interrupt Control 16−1 Pin Descriptions of the MSC1210 14−2 Chapter MSC1210 Description −1. MSC1210 Block DiagramMSC1210 Pin-Out −2. Pin Configuration of the MSC1210Pin # Name Description −1. Pin Descriptions of the MSC1210Pin # Name Description −1 Pin Descriptions of the MSC1210AD7 1 I/O Ports P0, P1, P2, and P3Port Port Oscillator Inputs XTAL1 and XTAL2 Reset Line RST Address Latch Enable ALEProgram Store Enable Psen External Access EA −3. MSC1210 Timing Compared to Standard 8051 Timing Enhanced 8051 CoreFamily Device Compatibility Flash MemoryHigh Performance Analog Functions High-Performance Peripherals Description Program Memory Data Memory Internal RAM Program Memory DescriptionMSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 −1. Program and Data Memory SizeData Memory −2. Program and Data Memory AddressesOn-Chip Extended Static RAM Sram External Data Memory On-Chip Flash Data Memory−2. MSC1210 Memory Map Register Bank Internal RAMRegister Banks StackBit Memory Or execute Special Function Register SFR Memory Defines the MSC1210 SFRs SCON0 −1. SFR Names and AddressesReferencing Bits of SFRs Referencing SFRsSFR Types Bit−Addressable SFRsSFR Definitions SFR Definitions SFR Definitions SFR Definitions Can be generated automatically by the MSC1210 P0DDRL/P0DDRH Port 0 Data Direction Low/High Byte, Addresses GCL/GCM/GCH Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H SFR Definitions SFR Definitions SFR Definitions Describes the basic register functions of the MSC1210 ADC Registers AccumulatorProgram Counter PC RegisterStack Pointer SP Data Pointer DPTR0/DPTR1Describes the various addressing modes of the MSC1210 Mode Example Immediate Addressing−1. MSC1210 Addressing Modes Direct Addressing Indirect Addressing Movx A,@DPTR Movx @DPTR,A External Direct AddressingCode Indirect Adressing External Indirect AddressingDescribes the program flow of the MSC1210 ADC Direct Jumps Conditional BranchingConsider the example Direct Calls Returns From RoutinesInterrupts Description System Timers Startup Timing −1. Standard 8051 Timing System Timing System Timers −2. MSC1210 Timing Chain and Clock Control Milliseconds Timer Microseconds Timer−4. System Timing Interrupt Control One Hundred Millisecond Clock Normal-Mode Power-On Reset Timing Flash Programming Mode Power-On Reset TimingStartup Timing Psen Symbol Parameter Min Max UnitDescribes the timers of the MSC1210 ADC How Does a Timer Count? Using Timers to Measure TimeHow Long Does a Timer Take to Count? RD or WR Strobe Width Width ∝sMovx Duration SYS CLKs At 12MHz Timer SFRs −1. Timer Conrol SFRsSFR Name Description SFR Address Bit Addressable? Mode Tmod SFRTxM1 TxM0 Timer Description of Timer Mode −2. Timer Modes and Usage−3. Example of 8-Bit Auto-Reload InstructionCycle Bit Name Bit Address Explanation of Function Timer Tcon SFR−4. Tcon 88 H SFR Reading the Timer Initializing a TimerDetecting Timer Overflow Timing the Length of Events Using Timers as Event Counters 1 T2CON SFR Using TimerTimer 2 in Auto-Reload Mode Timer 2 in Capture Mode Timer 2 as a Baud Rate Generator Describes serial communication using the MSC1210 ADC Description Function Length Period Setting the Serial Port ModeMode −1. SM0 and SM1 Function DefinitionsHigh four bits bits 4 through 7 are configuration bits Serial Mode 0 Synchronous Half-DuplexSerial Mode 1 Asynchronous Full-Duplex −2. Serial Port Mode 0 Receive Timing-High Speed Operation−3. Serial Port Mode 1 Transmit Timing BaudRate + 32 @ Timer1Overflow −2. Common Baud Rates Using TimerBaudRate + Timer2Overflow BaudRate + 12 @ 256 * TH1Serial Mode 2 Asynchronous Full-Duplex −3. Common Baud Rates Using TimerRcap 2H Rcap 2L + Baud Rate RCAP2HRCAP2L @ 11.0592MHz f OSCBaudRate + 2SMOD @ fOSC −6. Serial Port 0 Mode 2 Receive Timing−7. Serial Port 0 Mode 3 Transmit Timing Serial Mode 3 Asynchronous Full-DuplexSetting the Serial Port Mode −4. Mode 0 Commonly Used Baud Rates Setting the Serial Port Baud RateTH1 = 256 − Crystal / 192 / Baud Baud RateDesired Baud −5. Baud Rate Settings for Timer−6. Baud Rate Settings for Timer Writing to the Serial PortBaud Rate 33MHz clk 25MHz clk 11.0592MHz clk Kb/s Reading the Serial Port Describes the interrupts of the MSC1210 ADC JNB TF0,SKIPTOGGLE Interrupt/Event Addr Priority Flag Enable Priority Control Events That Can Trigger Interrupts−1.Interrupt Sources 10-4 −2.IE A8 H SFR Enabling Interrupts−3.EICON D8 H SFR −4.EIE E8 H SFRPolling Sequence Interrupt Priorities −5.IP B8 H SFR−6.EIP F8 H SFR Exiting Interrupts Interrupt TriggeringTypes of Interrupts Serial InterruptsExternal Interrupts Bit Name Explanation of Function −7.EXIF 91 H SFRTimer Interrupts Watchdog InterruptAuxiliary Interrupts −8.Clearing Auxiliary Interrupts −9.AIE A6 H SFRAux Interrupt Type Method to Clear Interrupt −10. Aistat A7 H SFR −11. PAI A5 H SFRBit Name Explanation of Function Clear Interrupt PAIx Bits Explanation of Interrupt/Event −12. PPI Bits of PAI SFR−13. EWU C6 H SFR Waking Up from Idle ModePush PSW Register ProtectionPush R0 Error − Invalid instruction Common Problems with Interrupts Description 11-2 Tone Generator 11-3PWM Generator 11-5 −1. Block Diagram ToneFrequency +1 Tone GeneratorTone Generator Waveforms −3. Timing Diagram of Tone Generator in Staircase Mode−1. PWM Polarity Conditions PWM GeneratorDuty Cycle = PWM Period +1 − PWM Duty/PWM Period +1 Condition Duty Cycle−5. Timing Diagram of a PWM Waveform This can be expressed in code as Stmt ‘C’ Source Code Assembly Source Code −2. Configuring the PWM for Tone GenerationExample of PWM Tone Generation −3. Statement ExplanationsExample of PWM Tone Generation Idling −4. Configuring the PWM for Tone Generation with PWM Idling −5. Statement ExplanationsExplanation −6. PWM Timing Example of Updating PWM11-12 12-10 PGA DAC−1. MSC1210 Architecture Input Multiplexer −2. Input Multiplexer ConfigurationNegative Input Positive InputTemperature Sensor 12-6 MSB Burnout Current SourcesAnalog Input Input Buffer@ 10 ACLKFrequencyProgrammable Gain Amplifier PGA −1.PGA SettingsModulator Offset DAC−2.Calibration Mode Control Bits Calibration ModeCalibration −4. Filter Step Responses Digital Filter−5. Filter Frequency Responses −3.Filter Settling Multiplexing Channels−4.Output Data Rate and Channel Rate Samples to Discard Filter−5.Output Data Rate and Channel Rate 10x faster Voltage ReferenceSource Summation/Shifter RegisterShift Summation Count Summation CountADC Summation Mode Manual Summation ModeADC Summation with Shift Divide Mode Manual Shift Divide ModeInterrupt-Driven ADC Sampling Analog-to-Digital Converter 12-21 Syncronizing Multiple MSC1210 Devices Analog-to-Digital Converter 12-23 ADC Result + V REF Ratiometric MeasurementsPT100 ADC Result + R REF @ I OUTDifferential Vref 12-26 SPI Signals 13-5 Clock Phase and Polarity Controls 13-4SPI System Errors 13-6 Description 13-2Functional Description −1. SPI block diagram−2. SPI Clock/Data Timing Clock Phase and Polarity Controls Master In Slave Out SPI SignalsMaster Out Slave Serial ClockSPI System Errors Data Transfers −3. SPI Reset State13-8 −4. SPI Fifo Operation Fifo OperationCode Examples SPI Master Transfer in Fifo Mode using Interrupts 13-12 Watchdog Timer 14-4 Description 14-2Low-Voltage Detect 14-2 Low-Voltage Detect −1. Brownout Reset and Low-Voltage Detection−2.Comparator Specification Power Supply−1.Typical Sub-Circuit Current Consumption −3.Band Gap ParametersWatchdog Timer Hardware Configuration Watchdog TimerEnabling Watchdog Timer Watchdog Timer Resetting the Watchdog Timer Watchdog Timeout/Activation Disabling Watchdog TimerPower Optimization 15-9 Hardware Configuration 15-2Advanced Flash Memory 15-6 Breakpoint Generator 15-7Hardware Configuration Registers Hardware ConfigurationDFSEL2/1/0 Amount of Flash Data Memory Hardware Configuration Register 0 HCR0Hardware Configuration Register 1 HCR1 Accessing Configuration Memory in a User Program Hardware Configuration MemoryUpdating Interrupts with Reset Sector Lock Advanced Flash MemoryWrite Protecting Flash Program Memory Breakpoint Generator Configuring BreakpointsDisabling a Breakpoint Breakpoint Auxiliary InterruptPower Optimization Flash Memory as Data Memory Advanced Topics 15-11 Advanced Topics and Other Information Describes the 8052 Assembly Language Syntax Label and instruction Expressions Number BasesCharacters and Character Strings Operator Precedence−1.Order of Precedence for Mathematical Operators Order OperatorLjmp LABEL3 Changing Program Flow LJMP, SJMP, AjmpSubroutines LCALL, ACALL, RET MOV DestinationRegister,SourceValue Register Assignment MOVMOV R2,R1 Invalid MOV @R0,A Incrementing and Decrementing Registers INC, DEC Program Loops Djnz Setting, Clearing, and Moving Bits SETB, CLR, CPL, MOV 16-14 Bit-Based Decisions and Branching JB, JBC, JNB, JC, JNC Lcall Debouncekey Value Comparison CjneCheckless JC Aisless Less Than and Greater Than Comparison CjnePerforming Additions ADD, Addc Zero and Non-Zero Decisions JZ/JNZPerforming Additions ADD, Addc Performing Subtractions Subb Performing Multiplication MUL Performing Division DIV −1. Rotate Operations Shifting Bits RR, RRC, RL, RLC−2.Results of ANL Bit-Wise Logical Instructions ANL, ORL, XRL−3.Results of ORL −4.Results of XRLAssembly Language 16-25 Swapping Accumulator Nibbles Swap Exchanging Register Values XCHAdjusting Accumulator for BCD Addition DA Using the Stack PUSH/POP Assembly Language 16-29 Setting the Data Pointer Dptr MOV Dptr Reading and Writing External RAM/Data Memory Movx Lcall SUB Reading Code Memory/Tables MovcSUB INC a Using Jump Tables JMP @A+DPTR Describes the Keil simulator and its functions 17-2 Keil Simulator 17-3 −1. Timer/Counter 0 − Mode Timers−2. Timer/Counter Timer 0 & 1 Example−4. Timer/Counter 1 Mode Keil Simulator 17-7 17-8 Keil Simulator 17-9 17-10 Timer −1.Timer/Counter 2 Control BitsRegister Bit Toggle Box Name −7. Status of Watchdog Peripheral Watchdog Reset Facility Example 17-14 Keil Simulator 17-15 Clock Control System TimerAnalog-to-Digital Converter −8. Analog−to−Digital Converter Peripheral −9. Error Message −10. Accumulator/Shifter Peripheral Summation/Shifter17.8.1 ADC/Summation/Shifter Example 17-22 Keil Simulator 17-23 17-24 Keil Simulator 17-25 17-26 Keil Simulator 17-27 −11. summation/Shifter Peripheral Keil Simulator 17-29 −13. List Box for the Interrupt Peripheral Ports −14. Parallel Port 0 Contents Display Window−16. SPI Peripheral Window Serial Peripheral Interface SPIKeil Simulator 17-33 SPI Sample Code Keil Simulator 17-35 Serial Peripheral Interface SPI Keil Simulator 17-37 17.12 ∝Vision 2 Debug Program Example −17. Keil Debugger Serial Port I/O −18. Serial Channel 0 Communication Peripheral 17-42 Transmit Block Baud Rate Computation BaudRate + fOSCBaudRate + fOSC @ Receive Block Baud Rate Computation −19. Clock Control Peripheral Additional Resource Topic Appendix aAdditional Features in the MSC1210 Compared to Appendix B Figure B−1. MSC1210 Timing Chain and Clock Control MSC1210 Timing Chain and Clock Control DiagramAppendix C Address Routine Declarations Description Table C−1. Boot ROM RoutinesBoot ROM Routines Page Appendix D JB bitAddr,relAddr Ajmp pg1Addr 8052 Instruction-Set Quick-Reference GuideDescription Instruction Set Appendix EDescription Acall 8052 Instruction SetAbsolute Call within 2k Block Acall codeAddressADD, Addc Add Value, Add Value with CarryADD A,operand Ajmp Absolute Jump within 2k BlockAjmp codeAddress ANL BitwiseANL operand1,operand2 CLR Compare and Jump if Not EqualClear Register Cjne operand1,operand2,reladdrCPL Decimal Adjust AccumulatorComplement Register CPL operandCarry flag is not set when the value rolls over from 0 to Decrementing the value causes it to reset to 255 0xFFHDEC register See also INC, SubbDjnz register,relAddr Decrement and Jump if Not ZeroINC Increment ReisterINC register JBC Jump if Bit SetJump if Bit Set and Clear Bit Jump if Carry SetJMP JNBJNC JNZ LcallLjmp MOV operand1, operand2 Not affected See also MOVC, MOVX, XCH, XCHD, PUSH, POPMOV bit1,bit2 MOV Move into/out of Internal RAMMOV operand1,operand2 MOV Dptr MovcMovx Multiply Accumulator by B MULNOP No OperationORL Bitwise orSyntax ORL operand1,operand2 Pop Value from Stack POPPush Push Value onto StackReturn from Subroutine RETReti Return from InterruptRLC RRCSetb Short Jump SjmpSubb Subtract from Accumulator with BorrowSwap XCHXchd Bitwise Exclusive or XRLInstructions OpCode Bytes Cycles Flags ??? 0xA5 UndefinedAppendix F Extended Interrupt Enable EIE Enable Interrupt Control EiconEX2-External 2 Interrupt Enable Bit Addressable SFRs alphabeticalExtended Interrupt Priority EIP Interrupt Enable IEPort 0 P0 Interrupt Priority IPPort 2 P2 Port 1 P1Port 3 P3 Register Bank Register Bank Addresses Program Status Word PSWSerial Control Scon Serial Mode Description BaudTcon Timer Control TconT2CON Timer 2 Control T2CONAppendix G SFR Name Description SFR Address Hex SFR/Address Cross-ReferenceSFRs/Address Cross-Reference Guide alphabetical Spircon