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Texas Instruments MSC1210 manual 1. Block Diagram

Models: MSC1210

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Description

11.1 Description

The pulse width modulator (PWM) has two modes: one mode functions as a tone generator and the the other mode functions as a pulse width modulator.

Figure 11−1. Block Diagram

The PWM/tone generator is controlled and configured by a number of SFRs, the primary being the PWM Configuration (PWMCON, A1H) SFR.

The individual bits of PWMCON have the following functions:

	7	6	5	4	3	2	1	0	Reset Value

SFR A1H	—	—	PPOL	PWMSEL	SPDSEL	TPCNTL.2	TPCNTL.1	TPCNTL.0	00H

PPOL (bit 5)— Period Polarity. Specifies the level of the PWM pulse.

0:ON period. PWM Duty register programs the ON period.

1:OFF period. PWM Duty register programs the OFF period.

PWMSEL(bit 4)— PWM Register Select. Select which 16-bit register is ac- cessed by PWMLOW/PWMHIGH.

0:Period.

1:Duty.

SPDSEL(bit 3)— Speed Select.

0:1MHz (ONEUSEC Clock).

1:SYSCLK.

TPCNTL(bits 2-0)—Tone Generator/Pulse Width Modulator Control.

TPCNTL.2	TPCNTL.1	TPCNTL.0	Mode

0	0	0	Disable (default)

0	0	1	PWM

0	1	1	Tone—square

1	1	1	Tone—staircase

11-2

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Texas Instruments MSC1210 manual 1. Block Diagram

Contents

User’s Guide Important Notice Introduction to the MSC1210 MSC1210 Memory OrganizationBasic Registers Addressing Modes System TimingSerial Communication Pulse Width Modulator/Tone Generator Analog-to-Digital ConverterSerial Peripheral Interface SPI Additional MSC1210 HardwareAdditional Resource Boot ROM Routines Additional Features in the MSC1210 Compared toClock Timing Diagram Instruction-Set Quick-Reference GuideSPI/PWM/Flash Write Timing System Timing Interrupt Control 16−1 Pin Descriptions of the MSC1210 14−2 Chapter −1. MSC1210 Block Diagram MSC1210 Description−2. Pin Configuration of the MSC1210 MSC1210 Pin-Out−1. Pin Descriptions of the MSC1210 Pin # Name Description−1 Pin Descriptions of the MSC1210 Pin # Name Description1 I/O Ports P0, P1, P2, and P3 AD7Port Port Oscillator Inputs XTAL1 and XTAL2 Reset Line RST Address Latch Enable ALEProgram Store Enable Psen External Access EA Enhanced 8051 Core −3. MSC1210 Timing Compared to Standard 8051 TimingFamily Device Compatibility Flash MemoryHigh Performance Analog Functions High-Performance Peripherals Description Program Memory Data Memory Internal RAM Description Program Memory−1. Program and Data Memory Size MSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5Data Memory −2. Program and Data Memory AddressesOn-Chip Extended Static RAM Sram On-Chip Flash Data Memory External Data MemoryInternal RAM −2. MSC1210 Memory Map Register BankStack Register BanksBit Memory Or execute Special Function Register SFR Memory Defines the MSC1210 SFRs −1. SFR Names and Addresses SCON0Referencing SFRs Referencing Bits of SFRsBit−Addressable SFRs SFR TypesSFR Definitions SFR Definitions SFR Definitions SFR Definitions Can be generated automatically by the MSC1210 P0DDRL/P0DDRH Port 0 Data Direction Low/High Byte, Addresses GCL/GCM/GCH Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H SFR Definitions SFR Definitions SFR Definitions Describes the basic register functions of the MSC1210 ADC Accumulator RegistersRegister Program Counter PCData Pointer DPTR0/DPTR1 Stack Pointer SPDescribes the various addressing modes of the MSC1210 Mode Example Immediate Addressing−1. MSC1210 Addressing Modes Direct Addressing Indirect Addressing External Direct Addressing Movx A,@DPTR Movx @DPTR,AExternal Indirect Addressing Code Indirect AdressingDescribes the program flow of the MSC1210 ADC Conditional Branching Direct JumpsConsider the example Direct Calls Returns From RoutinesInterrupts Description System Timers Startup Timing −1. Standard 8051 Timing System Timing System Timers −2. MSC1210 Timing Chain and Clock Control Microseconds Timer Milliseconds Timer−4. System Timing Interrupt Control One Hundred Millisecond Clock Normal-Mode Power-On Reset Timing Flash Programming Mode Power-On Reset TimingStartup Timing Symbol Parameter Min Max Unit PsenDescribes the timers of the MSC1210 ADC How Does a Timer Count? Using Timers to Measure TimeHow Long Does a Timer Take to Count? RD or WR Strobe Width Width ∝sMovx Duration SYS CLKs At 12MHz Timer SFRs −1. Timer Conrol SFRsSFR Name Description SFR Address Bit Addressable? Tmod SFR Mode−2. Timer Modes and Usage TxM1 TxM0 Timer Description of Timer Mode−3. Example of 8-Bit Auto-Reload InstructionCycle Bit Name Bit Address Explanation of Function Timer Tcon SFR−4. Tcon 88 H SFR Initializing a Timer Reading the TimerDetecting Timer Overflow Timing the Length of Events Using Timers as Event Counters Using Timer 1 T2CON SFRTimer 2 in Auto-Reload Mode Timer 2 in Capture Mode Timer 2 as a Baud Rate Generator Describes serial communication using the MSC1210 ADC Description Setting the Serial Port Mode Function Length Period−1. SM0 and SM1 Function Definitions ModeSerial Mode 0 Synchronous Half-Duplex High four bits bits 4 through 7 are configuration bits−2. Serial Port Mode 0 Receive Timing-High Speed Operation Serial Mode 1 Asynchronous Full-Duplex−3. Serial Port Mode 1 Transmit Timing BaudRate + Timer2Overflow −2. Common Baud Rates Using TimerBaudRate + 32 @ Timer1Overflow BaudRate + 12 @ 256 * TH1Rcap 2H Rcap 2L + −3. Common Baud Rates Using TimerSerial Mode 2 Asynchronous Full-Duplex Baud Rate RCAP2HRCAP2L @ 11.0592MHz f OSC−6. Serial Port 0 Mode 2 Receive Timing BaudRate + 2SMOD @ fOSCSerial Mode 3 Asynchronous Full-Duplex −7. Serial Port 0 Mode 3 Transmit TimingSetting the Serial Port Mode TH1 = 256 − Crystal / 192 / Baud Setting the Serial Port Baud Rate−4. Mode 0 Commonly Used Baud Rates Baud Rate−5. Baud Rate Settings for Timer Desired Baud−6. Baud Rate Settings for Timer Writing to the Serial PortBaud Rate 33MHz clk 25MHz clk 11.0592MHz clk Kb/s Reading the Serial Port Describes the interrupts of the MSC1210 ADC JNB TF0,SKIPTOGGLE Interrupt/Event Addr Priority Flag Enable Priority Control Events That Can Trigger Interrupts−1.Interrupt Sources 10-4 −3.EICON D8 H SFR Enabling Interrupts−2.IE A8 H SFR −4.EIE E8 H SFRPolling Sequence Interrupt Priorities −5.IP B8 H SFR−6.EIP F8 H SFR Interrupt Triggering Exiting InterruptsTypes of Interrupts Serial InterruptsExternal Interrupts −7.EXIF 91 H SFR Bit Name Explanation of FunctionTimer Interrupts Watchdog InterruptAuxiliary Interrupts −8.Clearing Auxiliary Interrupts −9.AIE A6 H SFRAux Interrupt Type Method to Clear Interrupt −10. Aistat A7 H SFR −11. PAI A5 H SFRBit Name Explanation of Function Clear Interrupt −12. PPI Bits of PAI SFR PAIx Bits Explanation of Interrupt/EventWaking Up from Idle Mode −13. EWU C6 H SFRRegister Protection Push PSWPush R0 Error − Invalid instruction Common Problems with Interrupts Description 11-2 Tone Generator 11-3PWM Generator 11-5 −1. Block Diagram Tone Generator ToneFrequency +1−3. Timing Diagram of Tone Generator in Staircase Mode Tone Generator WaveformsDuty Cycle = PWM Period +1 − PWM Duty/PWM Period +1 PWM Generator−1. PWM Polarity Conditions Condition Duty Cycle−5. Timing Diagram of a PWM Waveform This can be expressed in code as Example of PWM Tone Generation −2. Configuring the PWM for Tone GenerationStmt ‘C’ Source Code Assembly Source Code −3. Statement ExplanationsExample of PWM Tone Generation Idling −4. Configuring the PWM for Tone Generation with PWM Idling −5. Statement ExplanationsExplanation Example of Updating PWM −6. PWM Timing11-12 PGA DAC 12-10−1. MSC1210 Architecture −2. Input Multiplexer Configuration Input MultiplexerPositive Input Negative InputTemperature Sensor 12-6 Burnout Current Sources MSB@ 10 Input BufferAnalog Input ACLKFrequency−1.PGA Settings Programmable Gain Amplifier PGAOffset DAC Modulator−2.Calibration Mode Control Bits Calibration ModeCalibration Digital Filter −4. Filter Step Responses−5. Filter Frequency Responses −4.Output Data Rate and Channel Rate Multiplexing Channels−3.Filter Settling Samples to Discard FilterVoltage Reference −5.Output Data Rate and Channel Rate 10x fasterSummation/Shifter Register SourceSummation Count Shift Summation CountManual Summation Mode ADC Summation ModeManual Shift Divide Mode ADC Summation with Shift Divide ModeInterrupt-Driven ADC Sampling Analog-to-Digital Converter 12-21 Syncronizing Multiple MSC1210 Devices Analog-to-Digital Converter 12-23 PT100 Ratiometric MeasurementsADC Result + V REF ADC Result + R REF @ I OUTDifferential Vref 12-26 SPI System Errors 13-6 Clock Phase and Polarity Controls 13-4SPI Signals 13-5 Description 13-2−1. SPI block diagram Functional Description−2. SPI Clock/Data Timing Clock Phase and Polarity Controls Master Out Slave SPI SignalsMaster In Slave Out Serial ClockSPI System Errors −3. SPI Reset State Data Transfers13-8 Fifo Operation −4. SPI Fifo OperationCode Examples SPI Master Transfer in Fifo Mode using Interrupts 13-12 Watchdog Timer 14-4 Description 14-2Low-Voltage Detect 14-2 −1. Brownout Reset and Low-Voltage Detection Low-Voltage Detect−1.Typical Sub-Circuit Current Consumption Power Supply−2.Comparator Specification −3.Band Gap ParametersWatchdog Timer Watchdog Timer Hardware ConfigurationEnabling Watchdog Timer Watchdog Timer Resetting the Watchdog Timer Disabling Watchdog Timer Watchdog Timeout/ActivationAdvanced Flash Memory 15-6 Hardware Configuration 15-2Power Optimization 15-9 Breakpoint Generator 15-7Hardware Configuration Hardware Configuration RegistersHardware Configuration Register 0 HCR0 DFSEL2/1/0 Amount of Flash Data MemoryHardware Configuration Register 1 HCR1 Hardware Configuration Memory Accessing Configuration Memory in a User ProgramUpdating Interrupts with Reset Sector Lock Advanced Flash MemoryWrite Protecting Flash Program Memory Configuring Breakpoints Breakpoint GeneratorBreakpoint Auxiliary Interrupt Disabling a BreakpointPower Optimization Flash Memory as Data Memory Advanced Topics 15-11 Advanced Topics and Other Information Describes the 8052 Assembly Language Syntax Label and instruction Number Bases Expressions−1.Order of Precedence for Mathematical Operators Operator PrecedenceCharacters and Character Strings Order OperatorChanging Program Flow LJMP, SJMP, Ajmp Ljmp LABEL3Subroutines LCALL, ACALL, RET Register Assignment MOV MOV DestinationRegister,SourceValueMOV R2,R1 Invalid MOV @R0,A Incrementing and Decrementing Registers INC, DEC Program Loops Djnz Setting, Clearing, and Moving Bits SETB, CLR, CPL, MOV 16-14 Bit-Based Decisions and Branching JB, JBC, JNB, JC, JNC Value Comparison Cjne Lcall DebouncekeyLess Than and Greater Than Comparison Cjne Checkless JC AislessZero and Non-Zero Decisions JZ/JNZ Performing Additions ADD, AddcPerforming Additions ADD, Addc Performing Subtractions Subb Performing Multiplication MUL Performing Division DIV Shifting Bits RR, RRC, RL, RLC −1. Rotate Operations−3.Results of ORL Bit-Wise Logical Instructions ANL, ORL, XRL−2.Results of ANL −4.Results of XRLAssembly Language 16-25 Exchanging Register Values XCH Swapping Accumulator Nibbles SwapAdjusting Accumulator for BCD Addition DA Using the Stack PUSH/POP Assembly Language 16-29 Setting the Data Pointer Dptr MOV Dptr Reading and Writing External RAM/Data Memory Movx Reading Code Memory/Tables Movc Lcall SUBSUB INC a Using Jump Tables JMP @A+DPTR Describes the Keil simulator and its functions 17-2 Keil Simulator 17-3 Timers −1. Timer/Counter 0 − ModeTimer 0 & 1 Example −2. Timer/Counter−4. Timer/Counter 1 Mode Keil Simulator 17-7 17-8 Keil Simulator 17-9 17-10 Timer −1.Timer/Counter 2 Control BitsRegister Bit Toggle Box Name −7. Status of Watchdog Peripheral Watchdog Reset Facility Example 17-14 Keil Simulator 17-15 System Timer Clock ControlAnalog-to-Digital Converter −8. Analog−to−Digital Converter Peripheral −9. Error Message Summation/Shifter −10. Accumulator/Shifter Peripheral17.8.1 ADC/Summation/Shifter Example 17-22 Keil Simulator 17-23 17-24 Keil Simulator 17-25 17-26 Keil Simulator 17-27 −11. summation/Shifter Peripheral Keil Simulator 17-29 −13. List Box for the Interrupt Peripheral −14. Parallel Port 0 Contents Display Window PortsSerial Peripheral Interface SPI −16. SPI Peripheral WindowKeil Simulator 17-33 SPI Sample Code Keil Simulator 17-35 Serial Peripheral Interface SPI Keil Simulator 17-37 17.12 ∝Vision 2 Debug Program Example −17. Keil Debugger Serial Port I/O −18. Serial Channel 0 Communication Peripheral 17-42 Transmit Block Baud Rate Computation BaudRate + fOSCBaudRate + fOSC @ Receive Block Baud Rate Computation −19. Clock Control Peripheral Additional Resource Appendix a TopicAdditional Features in the MSC1210 Compared to Appendix B MSC1210 Timing Chain and Clock Control Diagram Figure B−1. MSC1210 Timing Chain and Clock ControlAppendix C Table C−1. Boot ROM Routines Address Routine Declarations DescriptionBoot ROM Routines Page Appendix D 8052 Instruction-Set Quick-Reference Guide JB bitAddr,relAddr Ajmp pg1AddrAppendix E Description Instruction SetDescription Absolute Call within 2k Block 8052 Instruction SetAcall Acall codeAddressADD, Addc Add Value, Add Value with CarryADD A,operand Ajmp Absolute Jump within 2k BlockAjmp codeAddress ANL BitwiseANL operand1,operand2 Clear Register Compare and Jump if Not EqualCLR Cjne operand1,operand2,reladdrComplement Register Decimal Adjust AccumulatorCPL CPL operandDEC register Decrementing the value causes it to reset to 255 0xFFHCarry flag is not set when the value rolls over from 0 to See also INC, SubbDecrement and Jump if Not Zero Djnz register,relAddrINC Increment ReisterINC register Jump if Bit Set and Clear Bit Jump if Bit SetJBC Jump if Carry SetJMP JNBJNC JNZ LcallLjmp MOV operand1, operand2 Not affected See also MOVC, MOVX, XCH, XCHD, PUSH, POPMOV bit1,bit2 MOV Move into/out of Internal RAMMOV operand1,operand2 MOV Dptr MovcMovx NOP MULMultiply Accumulator by B No OperationORL Bitwise orSyntax ORL operand1,operand2 Push POPPop Value from Stack Push Value onto StackReti RETReturn from Subroutine Return from InterruptRLC RRCSetb Subb SjmpShort Jump Subtract from Accumulator with BorrowSwap XCHXchd XRL Bitwise Exclusive orUndefined Instructions OpCode Bytes Cycles Flags ??? 0xA5Appendix F EX2-External 2 Interrupt Enable Enable Interrupt Control EiconExtended Interrupt Enable EIE Bit Addressable SFRs alphabeticalInterrupt Enable IE Extended Interrupt Priority EIPInterrupt Priority IP Port 0 P0Port 1 P1 Port 2 P2Port 3 P3 Program Status Word PSW Register Bank Register Bank AddressesSerial Mode Description Baud Serial Control SconTimer Control Tcon TconTimer 2 Control T2CON T2CONAppendix G SFR/Address Cross-Reference SFR Name Description SFR Address HexSFRs/Address Cross-Reference Guide alphabetical Spircon