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Texas Instruments MSC1210 manual Description 14-2, Low-Voltage Detect 14-2, Watchdog Timer 14-4

Models: MSC1210

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Chapter 14

Chapter 14 describes addtional hardware on the MSC1210 ADC.

Topic		Page

14.1	Description	. 14-2
14.2	Low-Voltage Detect	. 14-2
14.3	Watchdog Timer	. 14-4

14-1

Image 175

Texas Instruments MSC1210 manual Description 14-2, Low-Voltage Detect 14-2, Watchdog Timer 14-4

Contents

User’s Guide Important Notice MSC1210 Memory Organization Introduction to the MSC1210Basic Registers System Timing Addressing ModesSerial Communication Analog-to-Digital Converter Pulse Width Modulator/Tone GeneratorAdditional MSC1210 Hardware Serial Peripheral Interface SPIAdditional Resource Instruction-Set Quick-Reference Guide Additional Features in the MSC1210 Compared toClock Timing Diagram Boot ROM RoutinesSPI/PWM/Flash Write Timing System Timing Interrupt Control 16−1 Pin Descriptions of the MSC1210 14−2 Chapter MSC1210 Description −1. MSC1210 Block DiagramMSC1210 Pin-Out −2. Pin Configuration of the MSC1210Pin # Name Description −1. Pin Descriptions of the MSC1210Pin # Name Description −1 Pin Descriptions of the MSC1210AD7 1 I/O Ports P0, P1, P2, and P3Port Port Oscillator Inputs XTAL1 and XTAL2 Address Latch Enable ALE Reset Line RSTProgram Store Enable Psen External Access EA −3. MSC1210 Timing Compared to Standard 8051 Timing Enhanced 8051 CoreFlash Memory Family Device CompatibilityHigh Performance Analog Functions High-Performance Peripherals Description Program Memory Data Memory Internal RAM Program Memory DescriptionMSC1210Y2 MSC1210Y3 MSC1210Y4 MSC1210Y5 −1. Program and Data Memory Size−2. Program and Data Memory Addresses Data MemoryOn-Chip Extended Static RAM Sram External Data Memory On-Chip Flash Data Memory−2. MSC1210 Memory Map Register Bank Internal RAMRegister Banks StackBit Memory Or execute Special Function Register SFR Memory Defines the MSC1210 SFRs SCON0 −1. SFR Names and AddressesReferencing Bits of SFRs Referencing SFRsSFR Types Bit−Addressable SFRsSFR Definitions SFR Definitions SFR Definitions SFR Definitions Can be generated automatically by the MSC1210 P0DDRL/P0DDRH Port 0 Data Direction Low/High Byte, Addresses GCL/GCM/GCH Gain Low/Middle/High Byte, Addresses D4H/D5H/D6H SFR Definitions SFR Definitions SFR Definitions Describes the basic register functions of the MSC1210 ADC Registers AccumulatorProgram Counter PC RegisterStack Pointer SP Data Pointer DPTR0/DPTR1Describes the various addressing modes of the MSC1210 Immediate Addressing Mode Example−1. MSC1210 Addressing Modes Direct Addressing Indirect Addressing Movx A,@DPTR Movx @DPTR,A External Direct AddressingCode Indirect Adressing External Indirect AddressingDescribes the program flow of the MSC1210 ADC Direct Jumps Conditional BranchingConsider the example Returns From Routines Direct CallsInterrupts Description System Timers Startup Timing −1. Standard 8051 Timing System Timing System Timers −2. MSC1210 Timing Chain and Clock Control Milliseconds Timer Microseconds Timer−4. System Timing Interrupt Control One Hundred Millisecond Clock Flash Programming Mode Power-On Reset Timing Normal-Mode Power-On Reset TimingStartup Timing Psen Symbol Parameter Min Max UnitDescribes the timers of the MSC1210 ADC Using Timers to Measure Time How Does a Timer Count?How Long Does a Timer Take to Count? Width Width ∝s RD or WR StrobeMovx Duration SYS CLKs At 12MHz −1. Timer Conrol SFRs Timer SFRsSFR Name Description SFR Address Bit Addressable? Mode Tmod SFRTxM1 TxM0 Timer Description of Timer Mode −2. Timer Modes and UsageInstruction −3. Example of 8-Bit Auto-ReloadCycle Tcon SFR Bit Name Bit Address Explanation of Function Timer−4. Tcon 88 H SFR Reading the Timer Initializing a TimerDetecting Timer Overflow Timing the Length of Events Using Timers as Event Counters 1 T2CON SFR Using TimerTimer 2 in Auto-Reload Mode Timer 2 in Capture Mode Timer 2 as a Baud Rate Generator Describes serial communication using the MSC1210 ADC Description Function Length Period Setting the Serial Port ModeMode −1. SM0 and SM1 Function DefinitionsHigh four bits bits 4 through 7 are configuration bits Serial Mode 0 Synchronous Half-DuplexSerial Mode 1 Asynchronous Full-Duplex −2. Serial Port Mode 0 Receive Timing-High Speed Operation−3. Serial Port Mode 1 Transmit Timing BaudRate + 12 @ 256 * TH1 −2. Common Baud Rates Using TimerBaudRate + 32 @ Timer1Overflow BaudRate + Timer2OverflowBaud Rate RCAP2HRCAP2L @ 11.0592MHz f OSC −3. Common Baud Rates Using TimerSerial Mode 2 Asynchronous Full-Duplex Rcap 2H Rcap 2L +BaudRate + 2SMOD @ fOSC −6. Serial Port 0 Mode 2 Receive Timing−7. Serial Port 0 Mode 3 Transmit Timing Serial Mode 3 Asynchronous Full-DuplexSetting the Serial Port Mode Baud Rate Setting the Serial Port Baud Rate−4. Mode 0 Commonly Used Baud Rates TH1 = 256 − Crystal / 192 / BaudDesired Baud −5. Baud Rate Settings for TimerWriting to the Serial Port −6. Baud Rate Settings for TimerBaud Rate 33MHz clk 25MHz clk 11.0592MHz clk Kb/s Reading the Serial Port Describes the interrupts of the MSC1210 ADC JNB TF0,SKIPTOGGLE Events That Can Trigger Interrupts Interrupt/Event Addr Priority Flag Enable Priority Control−1.Interrupt Sources 10-4 −4.EIE E8 H SFR Enabling Interrupts−2.IE A8 H SFR −3.EICON D8 H SFRPolling Sequence −5.IP B8 H SFR Interrupt Priorities−6.EIP F8 H SFR Exiting Interrupts Interrupt TriggeringSerial Interrupts Types of InterruptsExternal Interrupts Bit Name Explanation of Function −7.EXIF 91 H SFRWatchdog Interrupt Timer InterruptsAuxiliary Interrupts −9.AIE A6 H SFR −8.Clearing Auxiliary InterruptsAux Interrupt Type Method to Clear Interrupt −11. PAI A5 H SFR −10. Aistat A7 H SFRBit Name Explanation of Function Clear Interrupt PAIx Bits Explanation of Interrupt/Event −12. PPI Bits of PAI SFR−13. EWU C6 H SFR Waking Up from Idle ModePush PSW Register ProtectionPush R0 Error − Invalid instruction Common Problems with Interrupts Tone Generator 11-3 Description 11-2PWM Generator 11-5 −1. Block Diagram ToneFrequency +1 Tone GeneratorTone Generator Waveforms −3. Timing Diagram of Tone Generator in Staircase ModeCondition Duty Cycle PWM Generator−1. PWM Polarity Conditions Duty Cycle = PWM Period +1 − PWM Duty/PWM Period +1−5. Timing Diagram of a PWM Waveform This can be expressed in code as −3. Statement Explanations −2. Configuring the PWM for Tone GenerationStmt ‘C’ Source Code Assembly Source Code Example of PWM Tone GenerationExample of PWM Tone Generation Idling −5. Statement Explanations −4. Configuring the PWM for Tone Generation with PWM IdlingExplanation −6. PWM Timing Example of Updating PWM11-12 12-10 PGA DAC−1. MSC1210 Architecture Input Multiplexer −2. Input Multiplexer ConfigurationNegative Input Positive InputTemperature Sensor 12-6 MSB Burnout Current SourcesACLKFrequency Input BufferAnalog Input @ 10Programmable Gain Amplifier PGA −1.PGA SettingsModulator Offset DACCalibration Mode −2.Calibration Mode Control BitsCalibration −4. Filter Step Responses Digital Filter−5. Filter Frequency Responses Samples to Discard Filter Multiplexing Channels−3.Filter Settling −4.Output Data Rate and Channel Rate−5.Output Data Rate and Channel Rate 10x faster Voltage ReferenceSource Summation/Shifter RegisterShift Summation Count Summation CountADC Summation Mode Manual Summation ModeADC Summation with Shift Divide Mode Manual Shift Divide ModeInterrupt-Driven ADC Sampling Analog-to-Digital Converter 12-21 Syncronizing Multiple MSC1210 Devices Analog-to-Digital Converter 12-23 ADC Result + R REF @ I OUT Ratiometric MeasurementsADC Result + V REF PT100Differential Vref 12-26 Description 13-2 Clock Phase and Polarity Controls 13-4SPI Signals 13-5 SPI System Errors 13-6Functional Description −1. SPI block diagram−2. SPI Clock/Data Timing Clock Phase and Polarity Controls Serial Clock SPI SignalsMaster In Slave Out Master Out SlaveSPI System Errors Data Transfers −3. SPI Reset State13-8 −4. SPI Fifo Operation Fifo OperationCode Examples SPI Master Transfer in Fifo Mode using Interrupts 13-12 Description 14-2 Watchdog Timer 14-4Low-Voltage Detect 14-2 Low-Voltage Detect −1. Brownout Reset and Low-Voltage Detection−3.Band Gap Parameters Power Supply−2.Comparator Specification −1.Typical Sub-Circuit Current ConsumptionWatchdog Timer Hardware Configuration Watchdog TimerEnabling Watchdog Timer Watchdog Timer Resetting the Watchdog Timer Watchdog Timeout/Activation Disabling Watchdog TimerBreakpoint Generator 15-7 Hardware Configuration 15-2Power Optimization 15-9 Advanced Flash Memory 15-6Hardware Configuration Registers Hardware ConfigurationDFSEL2/1/0 Amount of Flash Data Memory Hardware Configuration Register 0 HCR0Hardware Configuration Register 1 HCR1 Accessing Configuration Memory in a User Program Hardware Configuration MemoryAdvanced Flash Memory Updating Interrupts with Reset Sector LockWrite Protecting Flash Program Memory Breakpoint Generator Configuring BreakpointsDisabling a Breakpoint Breakpoint Auxiliary InterruptPower Optimization Flash Memory as Data Memory Advanced Topics 15-11 Advanced Topics and Other Information Describes the 8052 Assembly Language Syntax Label and instruction Expressions Number BasesOrder Operator Operator PrecedenceCharacters and Character Strings −1.Order of Precedence for Mathematical OperatorsLjmp LABEL3 Changing Program Flow LJMP, SJMP, AjmpSubroutines LCALL, ACALL, RET MOV DestinationRegister,SourceValue Register Assignment MOVMOV R2,R1 Invalid MOV @R0,A Incrementing and Decrementing Registers INC, DEC Program Loops Djnz Setting, Clearing, and Moving Bits SETB, CLR, CPL, MOV 16-14 Bit-Based Decisions and Branching JB, JBC, JNB, JC, JNC Lcall Debouncekey Value Comparison CjneCheckless JC Aisless Less Than and Greater Than Comparison CjnePerforming Additions ADD, Addc Zero and Non-Zero Decisions JZ/JNZPerforming Additions ADD, Addc Performing Subtractions Subb Performing Multiplication MUL Performing Division DIV −1. Rotate Operations Shifting Bits RR, RRC, RL, RLC−4.Results of XRL Bit-Wise Logical Instructions ANL, ORL, XRL−2.Results of ANL −3.Results of ORLAssembly Language 16-25 Swapping Accumulator Nibbles Swap Exchanging Register Values XCHAdjusting Accumulator for BCD Addition DA Using the Stack PUSH/POP Assembly Language 16-29 Setting the Data Pointer Dptr MOV Dptr Reading and Writing External RAM/Data Memory Movx Lcall SUB Reading Code Memory/Tables MovcSUB INC a Using Jump Tables JMP @A+DPTR Describes the Keil simulator and its functions 17-2 Keil Simulator 17-3 −1. Timer/Counter 0 − Mode Timers−2. Timer/Counter Timer 0 & 1 Example−4. Timer/Counter 1 Mode Keil Simulator 17-7 17-8 Keil Simulator 17-9 17-10 −1.Timer/Counter 2 Control Bits TimerRegister Bit Toggle Box Name −7. Status of Watchdog Peripheral Watchdog Reset Facility Example 17-14 Keil Simulator 17-15 Clock Control System TimerAnalog-to-Digital Converter −8. Analog−to−Digital Converter Peripheral −9. Error Message −10. Accumulator/Shifter Peripheral Summation/Shifter17.8.1 ADC/Summation/Shifter Example 17-22 Keil Simulator 17-23 17-24 Keil Simulator 17-25 17-26 Keil Simulator 17-27 −11. summation/Shifter Peripheral Keil Simulator 17-29 −13. List Box for the Interrupt Peripheral Ports −14. Parallel Port 0 Contents Display Window−16. SPI Peripheral Window Serial Peripheral Interface SPIKeil Simulator 17-33 SPI Sample Code Keil Simulator 17-35 Serial Peripheral Interface SPI Keil Simulator 17-37 17.12 ∝Vision 2 Debug Program Example −17. Keil Debugger Serial Port I/O −18. Serial Channel 0 Communication Peripheral 17-42 BaudRate + fOSC Transmit Block Baud Rate ComputationBaudRate + fOSC @ Receive Block Baud Rate Computation −19. Clock Control Peripheral Additional Resource Topic Appendix aAdditional Features in the MSC1210 Compared to Appendix B Figure B−1. MSC1210 Timing Chain and Clock Control MSC1210 Timing Chain and Clock Control DiagramAppendix C Address Routine Declarations Description Table C−1. Boot ROM RoutinesBoot ROM Routines Page Appendix D JB bitAddr,relAddr Ajmp pg1Addr 8052 Instruction-Set Quick-Reference GuideDescription Instruction Set Appendix EDescription Acall codeAddress 8052 Instruction SetAcall Absolute Call within 2k BlockAdd Value, Add Value with Carry ADD, AddcADD A,operand Absolute Jump within 2k Block AjmpAjmp codeAddress Bitwise ANLANL operand1,operand2 Cjne operand1,operand2,reladdr Compare and Jump if Not EqualCLR Clear RegisterCPL operand Decimal Adjust AccumulatorCPL Complement RegisterSee also INC, Subb Decrementing the value causes it to reset to 255 0xFFHCarry flag is not set when the value rolls over from 0 to DEC registerDjnz register,relAddr Decrement and Jump if Not ZeroIncrement Reister INCINC register Jump if Carry Set Jump if Bit SetJBC Jump if Bit Set and Clear BitJNB JMPJNC Lcall JNZLjmp Not affected See also MOVC, MOVX, XCH, XCHD, PUSH, POP MOV operand1, operand2MOV bit1,bit2 Move into/out of Internal RAM MOVMOV operand1,operand2 Movc MOV DptrMovx No Operation MULMultiply Accumulator by B NOPBitwise or ORLSyntax ORL operand1,operand2 Push Value onto Stack POPPop Value from Stack PushReturn from Interrupt RETReturn from Subroutine RetiRRC RLCSetb Subtract from Accumulator with Borrow SjmpShort Jump SubbXCH SwapXchd Bitwise Exclusive or XRLInstructions OpCode Bytes Cycles Flags ??? 0xA5 UndefinedAppendix F Bit Addressable SFRs alphabetical Enable Interrupt Control EiconExtended Interrupt Enable EIE EX2-External 2 Interrupt EnableExtended Interrupt Priority EIP Interrupt Enable IEPort 0 P0 Interrupt Priority IPPort 2 P2 Port 1 P1Port 3 P3 Register Bank Register Bank Addresses Program Status Word PSWSerial Control Scon Serial Mode Description BaudTcon Timer Control TconT2CON Timer 2 Control T2CONAppendix G SFR Name Description SFR Address Hex SFR/Address Cross-ReferenceSFRs/Address Cross-Reference Guide alphabetical Spircon