Texas Instruments MSC1210 manual Data Pointer DPTR0/DPTR1, Stack Pointer SP

Data Pointer (DPTR0/DPTR1)

4.6 Data Pointer (DPTR0/DPTR1)

The data pointer (DPTR0/DPTR1) is the user-accessible 16-bit (2-byte) regis- ter of the MSC1210. The accumulator, R registers, and B register are all 1-byte values. The PC just described is a 16-bit value, but is not directly user-accessi- ble as a working register.

DPTR0/DPTR1, as the name suggests, are used to point to data. They are used by a number of commands that allow the MSC1210 to access data and code memory. When the MSC1210 accesses external memory, it accesses the memory at the address indicated by DPTR0/DPTR1.

Although DPTR0/DPTR1 is most often used to point to data in external memory or code memory, many developers take advantage of the fact that it is the only true 16-bit register available. It is often used to store 2-byte values that have nothing to do with memory locations. DPTR0 or DPTR1 is selected by SFR DPS.

4.7 Stack Pointer (SP)

The stack pointer (SP), like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The SP is used to indicate where the next value to be re- moved from the stack should be taken from.

When a value is pushed onto the stack, the MSC1210 first increments the val- ue of the SP and then stores the value at the resulting memory location.

When a value is popped off the stack, the MSC1210 returns the value from the memory location indicated by the SP, and then decrements the value of the SP.

This order of operation is important. When the MSC1210 is initialized, SP will be initialized to 07H. If a value is immediately pushed onto the stack, the value will be stored in internal RAM address 08H. This makes sense, taking into ac- count what was mentioned two paragraphs above. First the MSC1210 will in- crement the value of the SP (from 07H to 08H) and then will store the pushed value at that memory address (08H).

The SP is modified directly by the MSC1210 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used intrinsically whenever an inter- rupt is triggered (more on interrupts in Chapter 10—do not worry about them for now).

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