Texas Instruments TMS3320C5515 manuals

Car Audio and Video > Car Stereo System

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Texas Instruments TMS3320C5515 Manual

Texas Instruments TMS3320C5515 Manual

78 pages418.73 Kb

3Contents
- Preface
9Read This First
- About This Manual
- Notational Conventions
- Related Documentation From Texas Instruments
- Chapter 1
13System Control
- 1.1 Introduction
- 1.1.1 BlockDiagram
- 141.1.2 CPU Core
- 1.1.3 FFT Hardware Accelerator
- 151.1.4 Power Management
- 1.1.5 Peripherals
- 161.2 System Memory
- 1.2.1 Program/DataMemory Map
  - System Memory
  - 17Figure 1-2. DSP Memory Map
  - System Memory
  - 18Table 1-2. DARAM Blocks (continued)
- 201.2.2 I/O Memory Map
- 1.3 Device Clocking 1.3.1 Overview
  - Device Clocking
    - www.ti.com
      - Copyright 2010, Texas Instruments Incorporated
  - 22Figure 1-3. DSP Clocking Diagram
    - 22 SystemControl SPRUFX5AOctober 2010 Revised November 2010 SubmitDocumentation Feedback
- 231.3.2 Clock Domains
- 1.4 System Clock Generator 1.4.1 Overview
- 24( )
  - 1.4.2 Functional Description
  - 261.4.3 Configuration
  - 291.4.4 Clock Generator Registers
    - System Clock Generator
    - 32Table 1-17. Clock Configuration Register 1 (CCR1) Field Descriptions
    - Table 1-18. Clock Configuration Register 2 (CCR2) Field Descriptions
  - 331.5 Power Management 1.5.1 Overview
  - 1.5.2 Power Domains
    - Table 1-20. DSP Power Domains
  - 341.5.3 Clock Management
    - 36Figure 1-12. Idle Configuration Register (ICR) [0001h]
    - Table 1-21. Idle Configuration Register (ICR) Field Descriptions
    - 39Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions
    - 40Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued)
    - 41Table 1-25. Peripheral Clock Gating Configuration Register 2 (PCGCR2) Field Descriptions
  - 461.5.4 Static Power Management
    - Table 1-28. RTC Power Management Register (RTCPMGT) Field Descriptions
    - 47Table 1-29. RTC Interrupt Flag Register (RTCINTFL) Field Descriptions
    - 49Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A]
    - Figure 1-22. RAM Sleep Mode Control Register3 [0x1C2B]
    - Figure 1-23. RAM Sleep Mode Control Register4 [0x1C2C]
    - Figure 1-24. RAM Sleep Mode Control Register5 [0x1C2D]
  - 501.5.5 Power Configurations
    - Table 1-31. Power Configurations
  - 531.6 Interrupts
    - Interrupts
    - Table 1-32. Interrupt Table (continued)
  - 541.6.1 IFR and IER Registers
    - Table 1-33. IFR0 and IER0 Bit Descriptions
  - 551.6.2 InterruptTiming
  - 561.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]
  - 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers
  - 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers
  - 571.7 System Configuration and Control 1.7.1 Overview
  - 1.7.2 DeviceIdentification
  - 611.7.3 Device Configuration
    - 62Table 1-44. EBSR Register Bit Descriptions Field Descriptions
    - 64Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions
    - 65Figure 1-37. LDO Control Register (LDOCNTL) [7004h]
    - Table 1-46. LDOCNTL Register Bit Descriptions Field Descriptions
    - Table 1-47. LDO Controls Matrix
    - 67Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions
    - 68Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued)
    - Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions
    - 69Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued)
    - Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions
  - 701.7.4 DMA Controller Configuration
  - 731.7.5 Peripheral Reset
    - Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued)
  - 751.7.6 EMIF and USB Byte Access
    - 76Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses
    - Table 1-62. EMIF System Control Register (ESCR) Field Descriptions
  - 771.7.7 EMIF Clock Divider Register (ECDR) [1C26h]
    - 78IMPORTANT NOTICE

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